[FPGA][按键]独立按键驱动程序（消抖、触发信号）

代码

/*Copyright belong to afterdm@qq.com
 *Create data 2020/11/30
 *Last modified data 2020/12/5
 *Version v1.0.2.0
 *Descriptions button drive
 *Please delete within 24 hours without special circumstances
*/
module ButtonDrive(
	input				clk,
	input				rst,
	input		[3:0]	signal,
	output      [3:0]	flag,
	output	reg			align_clk
);
//define reg
reg drive_clk;
reg [15:0] drive_counter;

always @(posedge clk or negedge rst) begin
	if(rst == 1'b0) begin
		drive_clk <= 1'b0;
		align_clk <= 1'b0;
		drive_counter <= 16'b0;
	end
	else begin
		if(drive_counter == 16'd49_999) begin
            drive_counter <= 16'b0;
        end
        else begin
            drive_counter <= drive_counter + 1'b1;
        end
        if(drive_counter == 16'd24_999) begin
            drive_clk <= 1'b1;
        end
        else begin
            drive_clk <= 1'b0;
        end
        if(drive_counter == 16'd25_000) begin
            align_clk <= 1'b1;
        end
        else begin
            align_clk <= 1'b0;
        end
	end
end

ButtonModule b1(
	.clk	(drive_clk),
	.rst	(rst),
	.signal	(signal[0]),
	.flag	(flag[0])
);
ButtonModule b2(
	.clk	(drive_clk),
	.rst	(rst),
	.signal	(signal[1]),
	.flag	(flag[1])
);
ButtonModule b3(
	.clk	(drive_clk),
	.rst	(rst),
	.signal	(signal[2]),
	.flag	(flag[2])
);
ButtonModule b4(
	.clk	(drive_clk),
	.rst	(rst),
	.signal	(signal[3]),
	.flag	(flag[3])
);

endmodule

module ButtonModule (
	input				clk,
	input				rst,
	input				signal,
	output	reg			flag
);
//define reg
reg [3:0] keeptime;
reg [7:0] duration;

always @(posedge clk or negedge rst) begin
	if(rst == 1'b0) begin
		keeptime <= 4'b0;
		duration <= 8'b0;
	end
	else begin
		if(signal == 1'b0) begin
			if(keeptime == 4'd9) begin
				if(duration == 8'd249) begin
					duration <= 8'b0;
					flag <= 1'b1;
				end
				else begin
					duration <= duration + 1'b1;
					flag <= 1'b0;
				end
			end
			else begin
				keeptime <= keeptime + 1'b1;
			end
		end
		else begin
			flag <= 1'b0;
			keeptime <= 4'b0;
			duration <= 8'd249;
		end
	end
end

endmodule