[FPGA][DDS][IIC][ADDA][数码管][按键]函数发生器

最新推荐文章于 2024-05-30 20:15:33 发布
最新推荐文章于 2024-05-30 20:15:33 发布
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分类专栏： FPGA 文章标签： 芯片 算法 verilog fpga
本文为afterdm@qq.com原创文章，遵循 CC 4.0 BY-NC-SA 版权协议，转载请附上原文出处链接和本声明。
本文链接：https://blog.csdn.net/qq_41990237/article/details/110850384
版权

目录

开发环境

  • 正点原子开拓者FPGA开发板
  • Quartus 13.1

前置知识

按键检测
数码管显示
IIC
DDS

源代码

顶层代码

/*Copyright belong to afterdm@qq.com
 *Create data 2020/11/30
 *Last modified data 2020/12/8
 *Version v1.1.0.0
 *Descriptions Function Generator
 *Please delete within 24 hours without special circumstances
*/
module FunGenerator(
    input				clk,
	input				rst,
	input		[3:0]	button,
	output		[3:0]	showLED,
	output		[7:0]	valDigital,
	output		[5:0]	slcDigital,
	output				SCL,
	output				SDA
);

wire alignButton_clk;
wire [3:0] downFlag;
ButtonDrive BUTTON_DRIVE(
	.clk		(clk),
	.rst		(rst),
	.signal	    (button),
	.flag		(downFlag),
	.align_clk	(alignButton_clk)
);

wire [7:0] sampleNode;
DDSdrive DDS_DRIVE(
    .clk        		(clk),
    .rst        		(rst),
	.alignButton_clk	(alignButton_clk),
	.downFlag			(downFlag),
	.waveState			(showLED),
	.information		(digitalValue),
	.sampleNode			(sampleNode)
);

wire [19:0]	digitalValue;
digitalDrive DIGITAL_DRIVE(
	.clk		(clk),
	.rst		(rst),
	.value		(digitalValue),
	.valDigital	(valDigital),
	.slcDigital	(slcDigital)
);

wire alignIIC_clk;
wire comSignal, errorFlag;
IICdrive IIC_DRIVE(
	.clk		(clk),		//clk signal(50M)
	.rst		(rst),		//reset signal
	.wdata		(wdata),	//IIC write data
	.rdata		(),			//IIC read data
	.enaSignal	(enaSignal),//enable siginal
	.overFlag	(overFlag),	//over state(High level effective)
	.wrFlag		(wrFlag),	//write(0) read(1) state
	.comSignal	(comSignal),//complete signal
	.errorFlag	(errorFlag),//error signal(High level effective)
	.SCL		(SCL),		//IIC clk
	.SDA		(SDA),		//IIC data
	.align_clk	(alignIIC_clk)
);

wire enaSignal, overFlag, wrFlag;
wire [7:0] wdata;
FunGeneratorDrive FUNCTION_GENERATOR(
	.clk		(clk),
	.rst		(rst),
	.sampleNode	(sampleNode),
	.wdata		(wdata),
	.enaSignal	(enaSignal),
	.overFlag	(overFlag),
	.wrFlag		(wrFlag),
	.comSignal	(comSignal),
	.errorFlag	(errorFlag),
	.align_clk	(alignIIC_clk)
);

endmodule

按键代码

/*Copyright belong to afterdm@qq.com
 *Create data 2020/11/30
 *Last modified data 2020/12/5
 *Version v1.0.2.0
 *Descriptions button drive
 *Please delete within 24 hours without special circumstances
*/
module ButtonDrive(
	input				clk,
	input				rst,
	input		[3:0]	signal,
	output      [3:0]	flag,
	output	reg			align_clk
);
//define reg
reg drive_clk;
reg [15:0] drive_counter;

always @(posedge clk or negedge rst) begin
	if(rst == 1'b0) begin
		drive_clk <= 1'b0;
		align_clk <= 1'b0;
		drive_counter <= 16'b0;
	end
	else begin
		if(drive_counter == 16'd49_999) begin
            drive_counter <= 16'b0;
        end
        else begin
            drive_counter <= drive_counter + 1'b1;
        end
        if(drive_counter == 16'd24_999) begin
            drive_clk <= 1'b1;
        end
        else begin
            drive_clk <= 1'b0;
        end
        if(drive_counter == 16'd25_000) begin
            align_clk <= 1'b1;
        end
        else begin
            align_clk <= 1'b0;
        end
	end
end

ButtonModule b1(
	.clk	(drive_clk),
	.rst	(rst),
	.signal	(signal[0]),
	.flag	(flag[0])
);
ButtonModule b2(
	.clk	(drive_clk),
	.rst	(rst),
	.signal	(signal[1]),
	.flag	(flag[1])
);
ButtonModule b3(
	.clk	(drive_clk),
	.rst	(rst),
	.signal	(signal[2]),
	.flag	(flag[2])
);
ButtonModule b4(
	.clk	(drive_clk),
	.rst	(rst),
	.signal	(signal[3]),
	.flag	(flag[3])
);

endmodule

module ButtonModule (
	input				clk,
	input				rst,
	input				signal,
	output	reg			flag
);
//define reg
reg [3:0] keeptime;
reg [7:0] duration;

always @(posedge clk or negedge rst) begin
	if(rst == 1'b0) begin
		keeptime <= 4'b0;
		duration <= 8'b0;
	end
	else begin
		if(signal == 1'b0) begin
			if(keeptime == 4'd9) begin
				if(duration == 8'd249) begin
					duration <= 8'b0;
					flag <= 1'b1;
				end
				else begin
					duration <= duration + 1'b1;
					flag <= 1'b0;
				end
			end
			else begin
				keeptime <= keeptime + 1'b1;
			end
		end
		else begin
			flag <= 1'b0;
			keeptime <= 4'b0;
			duration <= 8'd249;
		end
	end
end

endmodule

数码管代码

/*Copyright belong to afterdm@qq.com
 *Create data 2020/11/30
 *Last modified data 2020/12/6
 *Version v1.0.2.1
 *Descriptions digital drive
 *Please delete within 24 hours without special circumstances
*/
module digitalDrive(
	input				clk,
	input				rst,
	input		[19:0]	value,
	output	reg	[ 7:0]	valDigital,
	output	reg	[ 5:0]	slcDigital
);

reg div;
reg [15:0] divCount;
reg [3:0] count;
reg [3:0] digit;
reg [19:0] digits;

always @(posedge clk or negedge rst) begin
	if(rst == 1'b0) begin
		div <= 1'b0;
		divCount <= 16'b0;
	end
	else begin
		if(divCount == 16'd24_999) begin
			divCount <= 16'b0;
			div <= ~div;
		end
		else begin
			divCount <= divCount + 1'b1;
		end
	end
end

always @(posedge div or negedge rst) begin
	if(rst == 1'b0) begin
		count <= 4'b0;
		digits <= 20'b0;
		slcDigital <= 6'h3e;
	end
	else begin
		count <= count == 4'd6 ? 0 : count + 1'd1;
		if(count == 4'd0) begin
			digits <= value;
		end
		else begin
			digit <= digits % 4'd10;
			if(count == 4'd1) begin
				slcDigital <= 6'h3e;
			end
			else begin
				slcDigital <= {slcDigital[4:0], slcDigital[5]};
			end
			digits <= digits / 4'd10;
		end
	end
end

always @(digit) begin
	valDigital = 8'hff;
	case(digit)
		4'd0	: begin
			valDigital = 8'hc0;
		end
		4'd1	: begin
			valDigital = 8'hf9;
		end
		4'd2	: begin
			valDigital = 8'ha4;
		end
		4'd3	: begin
			valDigital = 8'hb0;
		end
		4'd4	: begin
			valDigital = 8'h99;
		end
		4'd5	: begin
			valDigital = 8'h92;
		end
		4'd6	: begin
			valDigital = 8'h82;
		end
		4'd7	: begin
			valDigital = 8'hf8;
		end
		4'd8	: begin
			valDigital = 8'h80;
		end
		4'd9	: begin
			valDigital = 8'h90;
		end
		4'd10	: begin
			valDigital = 8'h88;
		end
		4'd11	: begin
			valDigital = 8'h83;
		end
		4'd12	: begin
			valDigital = 8'hc6;
		end
		4'd13	: begin
			valDigital = 8'ha1;
		end
		4'd14	: begin
			valDigital = 8'h86;
		end
		4'd15	: begin
			valDigital = 8'h8e;
		end
	endcase
end

endmodule

IIC代码

/*Copyright belong to afterdm@qq.com
 *Create data 2020/11/24
 *Last modified data 2020/12/3
 *Version v1.1.0.0
 *Descriptions IIC drive
 *Please delete within 24 hours without special circumstances
*/
/*
*/
module IICdrive(
	input				clk,		//clk signal(50M)
	input				rst,		//reset signal
	input		[7:0]	wdata,		//IIC write data
	output	reg	[7:0]	rdata,		//IIC read data
	input				enaSignal,	//enable siginal
	input				overFlag,	//over state(High level effective)
	input				wrFlag,		//write(0) read(1) state
	output	reg			comSignal,	//complete signal
	output	reg			errorFlag,	//error signal(High level effective)
	output	reg			SCL,		//IIC clk
	inout   			SDA,		//IIC data
	output	reg			align_clk
);
//define parameter
/******define state machine*****/
parameter STsetout	= 6'b00_0001;
parameter STbaction	= 6'b00_0010;
parameter STwrite	= 6'b00_0100;
parameter STread	= 6'b00_1000;
parameter STawait	= 6'b01_0000;
parameter STeaction	= 6'b10_0000;
//define reg
/******define div signal******/
reg drive_clk;
reg [6:0] drive_counter;
/******define state machine***/
reg [5:0] STstate, STnstate;
/******define state signal****/
reg STdone;
/******define count***********/
reg [7:0] IICcount;
/******define templete data***/  
reg [7:0] tempdata;
/******define IIC SDA(inout)**/
reg SDAswitch, SDAout;
//define wire
wire SDAin;
//define assign
assign SDA = (SDAswitch == 1'b1) ? (SDAout) : (1'bz);
assign SDAin = SDA;
//div clk (the input clk is 50M, generate 0.02M = 2vs)
always @(posedge clk or negedge rst) begin
	if(rst == 1'b0) begin
		drive_clk <= 1'b0;
		align_clk <= 1'b0;
		drive_counter <= 7'b0;
	end
	else begin
		if(drive_counter == 7'd99) begin
			drive_counter <= 7'b0;
		end
		else begin
			drive_counter <= drive_counter + 1'b1;
		end
		if(drive_counter == 7'd49) begin
			drive_clk <= 1'b1;
		end
		else begin
			drive_clk <= 1'b0;
		end
		if(drive_counter == 7'd50) begin
			align_clk <= 1'b1;
		end
		else begin
			align_clk <= 1'b0;
		end
	end
end
//state machine
always @(posedge drive_clk or negedge rst) begin
	if(rst == 1'b0) begin
		STstate <= STsetout;
	end
	else begin
		STstate <= STnstate;
	end
end
//state function
always @(*) begin
	STnstate = STsetout;
	case(STstate)
		STsetout	: begin
			if(enaSignal == 1'b1) begin
				STnstate = STbaction;
			end
			else begin
				STnstate = STsetout;
			end
		end
        STbaction   : begin
            if(STdone == 1'b1) begin
                STnstate = STwrite;
            end
            else begin
                STnstate = STbaction;
            end
        end
		STwrite		: begin
			if(STdone == 1'b1) begin
				if(errorFlag == 1'b1) begin
					STnstate = STeaction;
				end
				else begin
					STnstate = STawait;
				end
			end
			else begin
				STnstate = STwrite;
			end
		end
		STread		: begin
			if(STdone == 1'b1) begin
				STnstate = STawait;
			end
			else begin
				STnstate = STread;
			end
		end
        STawait     : begin
			if(enaSignal == 1'b1) begin
				if(overFlag == 1'b1) begin
					STnstate = STeaction;
				end
				else begin
					if(wrFlag == 1'b0) begin
						STnstate = STwrite;
					end
					else begin
						STnstate = STread;
					end
				end
			end
			else begin
				STnstate = STawait;
			end
        end
		STeaction	: begin
			if(STdone == 1'b1) begin
				STnstate = STsetout;
			end
			else begin
				STnstate = STeaction;
			end
		end
        default : begin end
	endcase
end
//handle function
always @(posedge drive_clk or negedge rst) begin
	if(rst == 1'b0) begin
		comSignal <= 1'b0;
		errorFlag <= 1'b0;
        SCL <= 1'b1;
        SDAout <= 1'b1;
		SDAswitch <= 1'b1;
		rdata <= 8'b0;
        STdone <= 1'b0;
		IICcount <= 8'b0;
	end
	else begin
		comSignal <= 1'b0;
		errorFlag <= 1'b0;
        STdone <= 1'b0;
		IICcount <= IICcount + 1'b1;
        
		case(STnstate)
			STsetout	: begin
				SDAswitch <= 1'b1;
				SCL <= 1'b1;
				SDAout <= 1'b1;
                IICcount <= 8'b0;
				comSignal <= 1'b1;
			end
            STbaction   : begin
				case(IICcount)
					2'd0 : begin
						SDAout <= 1'b0;
					end
					2'd1 : begin
						SCL <= 1'b0;
						IICcount <= 8'b0;
						STdone <= 1'b1;
					end
					default : begin end
				endcase
            end
			//cycle : SCL_LO -> outdata -> SCL_HI
			STwrite		: begin
				case(IICcount % 2'd3)
					2'd0 : begin
						case(IICcount)
							8'd0	: begin
								tempdata <= wdata;
							end
							8'd27	: begin
								//get subordinate response
								errorFlag <= 1'b0;
								STdone <= 1'b1;
							end
							default : begin
								SCL <= 1'b0;
								tempdata <= {tempdata[6:0], tempdata[7]};
							end
						endcase
					end
					2'd1 : begin
						case(IICcount)
							8'd25 : begin
							//three-state gate Prepare to input state
								SDAswitch <= 1'b0;
							end
							default : begin
								SDAout <= tempdata[7];
							end
						endcase
					end
					2'd2 : begin
						SCL <= 1'b1;
					end
					default : begin end
				endcase
			end
			//cycle : getdata -> SCL_LO -> SCL_HI
			STread		: begin
				case(IICcount % 2'd3)
					2'd0 : begin
						tempdata <= {tempdata[6:0], SDAin};
						case(IICcount)
							8'd0	: begin
								//three-state gate Prepare to input state
								SDAswitch <= 1'b0;
							end
							8'd24	: begin
								SDAout <= 1'b0;
							end
							default : begin end
						endcase
					end
					2'd1 : begin
						SCL <= 1'b0;
						if(IICcount == 8'd25) begin
							rdata <= tempdata;
							//three-state gate Prepare to output state
							SDAswitch <= 1'b1;
						end
						else begin end
					end
					2'd2 : begin
						SCL <= 1'b1;
						if(IICcount == 8'd26) begin
							STdone <= 1'b1;
						end
						else begin end
					end
					default : begin end
				endcase
			end
            STawait     : begin
                SDAswitch <= 1'b1;
				SCL <= 1'b0;
				SDAout <= 1'b0;
				IICcount <= 8'b0;
                comSignal <= 1'b1;
            end
			STeaction	: begin
				case(IICcount)
					8'd0 : begin
						SCL <= 1'b1;
					end
					8'd1 : begin
						SDAout <= 1'b1;
						STdone <= 1'b1;
					end
					default : begin end
				endcase
			end
            default : begin end
		endcase
	end
end
endmodule

adda芯片驱动代码

module FunGeneratorDrive(
	input				clk,
	input				rst,
	input		[7:0]	sampleNode,
	output	reg	[7:0]	wdata,
	output	reg			enaSignal,
	output	reg			overFlag,
	output	reg			wrFlag,
	input				comSignal,
	input				errorFlag,
	input				align_clk
);

parameter stIdle		= 5'b00001;
parameter stAddress		= 5'b00010;
parameter stCommand		= 5'b00100;
parameter stSenddata	= 5'b01000;
parameter stAwait		= 5'b10000;

reg [4:0] stState;

always @(posedge align_clk or negedge rst) begin
	if(rst == 1'b0) begin
		stState <= stIdle;
	end
	else begin
		enaSignal <= 1'b0;
		case(stState)
			stIdle		: begin
				stState <= stAddress;
			end
			stAddress	: begin
				wdata <= 8'h90;
				enaSignal <= 1'b1;
				overFlag <= 1'b0;
				wrFlag <= 1'b0;
				stState <= stCommand;
			end
			stCommand	: begin
				if(comSignal == 1'b1) begin
                    if(errorFlag == 1'b1) begin
                        stState <= stAwait;
                    end
                    else begin
                        wdata <= 8'h40;
                        enaSignal <= 1'b1;
                        stState <= stSenddata;
                    end
				end
				else begin end
			end
			stSenddata	: begin
				if(comSignal == 1'b1) begin
                    if(errorFlag == 1'b1) begin
                        stState <= stAwait;
                    end
                    else begin
                        wdata <= sampleNode;
					enaSignal <= 1'b1;
                    end
				end
				else begin
				end
			end
			default : begin end
		endcase
	end
end

endmodule

DDS算法代码

/*Copyright belong to afterdm@qq.com
 *Create data 2020/11/30
 *Last modified data 2020/12/7
 *Version v1.0.0.0
 *Descriptions DDS drive
 *Please delete within 24 hours without special circumstances
*/
module DDSdrive(
	input				clk,
    input               rst,
	input				alignButton_clk,
	input		[3:0]	downFlag,
	output	reg	[3:0]	waveState,
    output	reg	[19:0]  information,
    output	reg	[7:0]   sampleNode
);
//define parameter
parameter waveIdle		= 4'b0001;
parameter waveSine		= 4'b0010;
parameter waveSquare	= 4'b0100;
parameter waveRamp		= 4'b1000;
//define reg
reg drive_clk;
reg [4:0] drive_counter;

reg [17:0] DDSaddunit, DDSunit;
/*DDS 寄存器
 *[25:24]区块位 [23:18]采样位 [17:0]累加位
*/
reg [25:0] DDScounter;

reg [6:0] sampleNodedata;
//define wire

//驱动信号
always @(posedge clk or negedge rst) begin
	if(rst == 1'b0) begin
		drive_clk <= 1'b0;
		drive_counter <= 5'b0;
	end
	else begin
		if(drive_counter == 5'd24) begin
			drive_counter <= 5'b0;
			drive_clk <= ~drive_clk;
		end
		else begin
			drive_counter <= drive_counter + 1'b1;
		end
	end
end
//波形切换处理
always @(posedge downFlag[0] or negedge rst) begin
	if(rst == 1'b0) begin
		waveState <= waveIdle;
	end
	else begin
		waveState <= {waveState[2:0], waveState[3]};
	end
end
//波形频率处理
always @(posedge alignButton_clk or negedge rst) begin
	if(rst == 1'b0) begin
		DDSaddunit <= 18'd1;
	end
	else begin
		if(downFlag[1] == 1'b1) begin
			DDSaddunit <= DDSaddunit - DDSunit;
		end
		else begin end
		if(downFlag[3] == 1'b1) begin
			DDSaddunit <= DDSaddunit + DDSunit;
		end
		else begin end
	end
end
//波形频率单位处理
always @(posedge downFlag[2] or negedge rst) begin
	if(rst == 1'b0) begin
		DDSunit <= 18'd1;
	end
	else begin
		DDSunit <= {DDSunit[16:0], DDSunit[17]};
	end
end

always @(posedge drive_clk or negedge rst) begin
	if(rst == 1'b0) begin
		DDScounter <= 26'b0;
	end
	else begin
		DDScounter <= DDScounter + DDSaddunit;
	end
end

always @(posedge clk or negedge rst) begin
	if(rst == 1'b0) begin
		information <= 20'd1;
	end
	else begin
		if(downFlag[2] == 1'b1) begin
			information <= DDSunit;
		end
		else begin end
		if(downFlag[1] == 1'b1) begin
			information <= DDSaddunit;
		end
		else begin end
        if(downFlag[3] == 1'b1) begin
            information <= DDSaddunit;
        end
        else begin end
	end
end

always @(*) begin
	case(waveState)
		waveIdle	: begin
			sampleNode <= 8'hff;
		end
		waveSine	: begin
			case(DDScounter[25:18])
				8'd0	: sampleNode <= 8'd128;
				8'd1	: sampleNode <= 8'd131;
				8'd2	: sampleNode <= 8'd134;
				8'd3	: sampleNode <= 8'd137;
				8'd4	: sampleNode <= 8'd140;
				8'd5	: sampleNode <= 8'd144;
				8'd6	: sampleNode <= 8'd147;
				8'd7	: sampleNode <= 8'd150;
				8'd8	: sampleNode <= 8'd153;
				8'd9	: sampleNode <= 8'd156;
				8'd10	: sampleNode <= 8'd159;
				8'd11	: sampleNode <= 8'd162;
				8'd12	: sampleNode <= 8'd165;
				8'd13	: sampleNode <= 8'd168;
				8'd14	: sampleNode <= 8'd171;
				8'd15	: sampleNode <= 8'd174;
				8'd16	: sampleNode <= 8'd177;
				8'd17	: sampleNode <= 8'd179;
				8'd18	: sampleNode <= 8'd182;
				8'd19	: sampleNode <= 8'd185;
				8'd20	: sampleNode <= 8'd188;
				8'd21	: sampleNode <= 8'd191;
				8'd22	: sampleNode <= 8'd193;
				8'd23	: sampleNode <= 8'd196;
				8'd24	: sampleNode <= 8'd199;
				8'd25	: sampleNode <= 8'd201;
				8'd26	: sampleNode <= 8'd204;
				8'd27	: sampleNode <= 8'd206;
				8'd28	: sampleNode <= 8'd209;
				8'd29	: sampleNode <= 8'd211;
				8'd30	: sampleNode <= 8'd213;
				8'd31	: sampleNode <= 8'd216;
				8'd32	: sampleNode <= 8'd218;
				8'd33	: sampleNode <= 8'd220;
				8'd34	: sampleNode <= 8'd222;
				8'd35	: sampleNode <= 8'd224;
				8'd36	: sampleNode <= 8'd226;
				8'd37	: sampleNode <= 8'd228;
				8'd38	: sampleNode <= 8'd230;
				8'd39	: sampleNode <= 8'd232;
				8'd40	: sampleNode <= 8'd234;
				8'd41	: sampleNode <= 8'd235;
				8'd42	: sampleNode <= 8'd237;
				8'd43	: sampleNode <= 8'd239;
				8'd44	: sampleNode <= 8'd240;
				8'd45	: sampleNode <= 8'd241;
				8'd46	: sampleNode <= 8'd243;
				8'd47	: sampleNode <= 8'd244;
				8'd48	: sampleNode <= 8'd245;
				8'd49	: sampleNode <= 8'd246;
				8'd50	: sampleNode <= 8'd248;
				8'd51	: sampleNode <= 8'd249;
				8'd52	: sampleNode <= 8'd250;
				8'd53	: sampleNode <= 8'd250;
				8'd54	: sampleNode <= 8'd251;
				8'd55	: sampleNode <= 8'd252;
				8'd56	: sampleNode <= 8'd253;
				8'd57	: sampleNode <= 8'd253;
				8'd58	: sampleNode <= 8'd254;
				8'd59	: sampleNode <= 8'd254;
				8'd60	: sampleNode <= 8'd254;
				8'd61	: sampleNode <= 8'd255;
				8'd62	: sampleNode <= 8'd255;
				8'd63	: sampleNode <= 8'd255;
				8'd64	: sampleNode <= 8'd255;
				8'd65	: sampleNode <= 8'd255;
				8'd66	: sampleNode <= 8'd255;
				8'd67	: sampleNode <= 8'd255;
				8'd68	: sampleNode <= 8'd254;
				8'd69	: sampleNode <= 8'd254;
				8'd70	: sampleNode <= 8'd254;
				8'd71	: sampleNode <= 8'd253;
				8'd72	: sampleNode <= 8'd253;
				8'd73	: sampleNode <= 8'd252;
				8'd74	: sampleNode <= 8'd251;
				8'd75	: sampleNode <= 8'd250;
				8'd76	: sampleNode <= 8'd250;
				8'd77	: sampleNode <= 8'd249;
				8'd78	: sampleNode <= 8'd248;
				8'd79	: sampleNode <= 8'd246;
				8'd80	: sampleNode <= 8'd245;
				8'd81	: sampleNode <= 8'd244;
				8'd82	: sampleNode <= 8'd243;
				8'd83	: sampleNode <= 8'd241;
				8'd84	: sampleNode <= 8'd240;
				8'd85	: sampleNode <= 8'd239;
				8'd86	: sampleNode <= 8'd237;
				8'd87	: sampleNode <= 8'd235;
				8'd88	: sampleNode <= 8'd234;
				8'd89	: sampleNode <= 8'd232;
				8'd90	: sampleNode <= 8'd230;
				8'd91	: sampleNode <= 8'd228;
				8'd92	: sampleNode <= 8'd226;
				8'd93	: sampleNode <= 8'd224;
				8'd94	: sampleNode <= 8'd222;
				8'd95	: sampleNode <= 8'd220;
				8'd96	: sampleNode <= 8'd218;
				8'd97	: sampleNode <= 8'd216;
				8'd98	: sampleNode <= 8'd213;
				8'd99	: sampleNode <= 8'd211;
				8'd100	: sampleNode <= 8'd209;
				8'd101	: sampleNode <= 8'd206;
				8'd102	: sampleNode <= 8'd204;
				8'd103	: sampleNode <= 8'd201;
				8'd104	: sampleNode <= 8'd199;
				8'd105	: sampleNode <= 8'd196;
				8'd106	: sampleNode <= 8'd193;
				8'd107	: sampleNode <= 8'd191;
				8'd108	: sampleNode <= 8'd188;
				8'd109	: sampleNode <= 8'd185;
				8'd110	: sampleNode <= 8'd182;
				8'd111	: sampleNode <= 8'd179;
				8'd112	: sampleNode <= 8'd177;
				8'd113	: sampleNode <= 8'd174;
				8'd114	: sampleNode <= 8'd171;
				8'd115	: sampleNode <= 8'd168;
				8'd116	: sampleNode <= 8'd165;
				8'd117	: sampleNode <= 8'd162;
				8'd118	: sampleNode <= 8'd159;
				8'd119	: sampleNode <= 8'd156;
				8'd120	: sampleNode <= 8'd153;
				8'd121	: sampleNode <= 8'd150;
				8'd122	: sampleNode <= 8'd147;
				8'd123	: sampleNode <= 8'd144;
				8'd124	: sampleNode <= 8'd140;
				8'd125	: sampleNode <= 8'd137;
				8'd126	: sampleNode <= 8'd134;
				8'd127	: sampleNode <= 8'd131;
				8'd128	: sampleNode <= 8'd128;
				8'd129	: sampleNode <= 8'd125;
				8'd130	: sampleNode <= 8'd122;
				8'd131	: sampleNode <= 8'd119;
				8'd132	: sampleNode <= 8'd116;
				8'd133	: sampleNode <= 8'd112;
				8'd134	: sampleNode <= 8'd109;
				8'd135	: sampleNode <= 8'd106;
				8'd136	: sampleNode <= 8'd103;
				8'd137	: sampleNode <= 8'd100;
				8'd138	: sampleNode <= 8'd97;
				8'd139	: sampleNode <= 8'd94;
				8'd140	: sampleNode <= 8'd91;
				8'd141	: sampleNode <= 8'd88;
				8'd142	: sampleNode <= 8'd85;
				8'd143	: sampleNode <= 8'd82;
				8'd144	: sampleNode <= 8'd79;
				8'd145	: sampleNode <= 8'd77;
				8'd146	: sampleNode <= 8'd74;
				8'd147	: sampleNode <= 8'd71;
				8'd148	: sampleNode <= 8'd68;
				8'd149	: sampleNode <= 8'd65;
				8'd150	: sampleNode <= 8'd63;
				8'd151	: sampleNode <= 8'd60;
				8'd152	: sampleNode <= 8'd57;
				8'd153	: sampleNode <= 8'd55;
				8'd154	: sampleNode <= 8'd52;
				8'd155	: sampleNode <= 8'd50;
				8'd156	: sampleNode <= 8'd47;
				8'd157	: sampleNode <= 8'd45;
				8'd158	: sampleNode <= 8'd43;
				8'd159	: sampleNode <= 8'd40;
				8'd160	: sampleNode <= 8'd38;
				8'd161	: sampleNode <= 8'd36;
				8'd162	: sampleNode <= 8'd34;
				8'd163	: sampleNode <= 8'd32;
				8'd164	: sampleNode <= 8'd30;
				8'd165	: sampleNode <= 8'd28;
				8'd166	: sampleNode <= 8'd26;
				8'd167	: sampleNode <= 8'd24;
				8'd168	: sampleNode <= 8'd22;
				8'd169	: sampleNode <= 8'd21;
				8'd170	: sampleNode <= 8'd19;
				8'd171	: sampleNode <= 8'd17;
				8'd172	: sampleNode <= 8'd16;
				8'd173	: sampleNode <= 8'd15;
				8'd174	: sampleNode <= 8'd13;
				8'd175	: sampleNode <= 8'd12;
				8'd176	: sampleNode <= 8'd11;
				8'd177	: sampleNode <= 8'd10;
				8'd178	: sampleNode <= 8'd8;
				8'd179	: sampleNode <= 8'd7;
				8'd180	: sampleNode <= 8'd6;
				8'd181	: sampleNode <= 8'd6;
				8'd182	: sampleNode <= 8'd5;
				8'd183	: sampleNode <= 8'd4;
				8'd184	: sampleNode <= 8'd3;
				8'd185	: sampleNode <= 8'd3;
				8'd186	: sampleNode <= 8'd2;
				8'd187	: sampleNode <= 8'd2;
				8'd188	: sampleNode <= 8'd2;
				8'd189	: sampleNode <= 8'd1;
				8'd190	: sampleNode <= 8'd1;
				8'd191	: sampleNode <= 8'd1;
				8'd192	: sampleNode <= 8'd1;
				8'd193	: sampleNode <= 8'd1;
				8'd194	: sampleNode <= 8'd1;
				8'd195	: sampleNode <= 8'd1;
				8'd196	: sampleNode <= 8'd2;
				8'd197	: sampleNode <= 8'd2;
				8'd198	: sampleNode <= 8'd2;
				8'd199	: sampleNode <= 8'd3;
				8'd200	: sampleNode <= 8'd3;
				8'd201	: sampleNode <= 8'd4;
				8'd202	: sampleNode <= 8'd5;
				8'd203	: sampleNode <= 8'd6;
				8'd204	: sampleNode <= 8'd6;
				8'd205	: sampleNode <= 8'd7;
				8'd206	: sampleNode <= 8'd8;
				8'd207	: sampleNode <= 8'd10;
				8'd208	: sampleNode <= 8'd11;
				8'd209	: sampleNode <= 8'd12;
				8'd210	: sampleNode <= 8'd13;
				8'd211	: sampleNode <= 8'd15;
				8'd212	: sampleNode <= 8'd16;
				8'd213	: sampleNode <= 8'd17;
				8'd214	: sampleNode <= 8'd19;
				8'd215	: sampleNode <= 8'd21;
				8'd216	: sampleNode <= 8'd22;
				8'd217	: sampleNode <= 8'd24;
				8'd218	: sampleNode <= 8'd26;
				8'd219	: sampleNode <= 8'd28;
				8'd220	: sampleNode <= 8'd30;
				8'd221	: sampleNode <= 8'd32;
				8'd222	: sampleNode <= 8'd34;
				8'd223	: sampleNode <= 8'd36;
				8'd224	: sampleNode <= 8'd38;
				8'd225	: sampleNode <= 8'd40;
				8'd226	: sampleNode <= 8'd43;
				8'd227	: sampleNode <= 8'd45;
				8'd228	: sampleNode <= 8'd47;
				8'd229	: sampleNode <= 8'd50;
				8'd230	: sampleNode <= 8'd52;
				8'd231	: sampleNode <= 8'd55;
				8'd232	: sampleNode <= 8'd57;
				8'd233	: sampleNode <= 8'd60;
				8'd234	: sampleNode <= 8'd63;
				8'd235	: sampleNode <= 8'd65;
				8'd236	: sampleNode <= 8'd68;
				8'd237	: sampleNode <= 8'd71;
				8'd238	: sampleNode <= 8'd74;
				8'd239	: sampleNode <= 8'd77;
				8'd240	: sampleNode <= 8'd79;
				8'd241	: sampleNode <= 8'd82;
				8'd242	: sampleNode <= 8'd85;
				8'd243	: sampleNode <= 8'd88;
				8'd244	: sampleNode <= 8'd91;
				8'd245	: sampleNode <= 8'd94;
				8'd246	: sampleNode <= 8'd97;
				8'd247	: sampleNode <= 8'd100;
				8'd248	: sampleNode <= 8'd103;
				8'd249	: sampleNode <= 8'd106;
				8'd250	: sampleNode <= 8'd109;
				8'd251	: sampleNode <= 8'd112;
				8'd252	: sampleNode <= 8'd116;
				8'd253	: sampleNode <= 8'd119;
				8'd254	: sampleNode <= 8'd122;
				8'd255	: sampleNode <= 8'd125;
				default : begin end
			endcase
		end
		waveSquare	: begin
			sampleNode <= DDScounter[25] == 1'b1 ? 8'hff : 8'h00;
		end
		waveRamp	: begin
			sampleNode <= DDScounter[25] == 1'b0 ? {DDScounter[24:18], 1'b1} : {~DDScounter[24:18], 1'b1};
		end
		default : begin end
	endcase
end

endmodule
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