Hdlbits-水库问题

hdlbits 水库问题 Exams/ece241 2013 q4

这个问题给我最大的教训就是一定要好好学习英语，题目都看不懂，解释一下这道题目，水位是循序渐进变化的，当水位低于S1的时候，打开所有水阀，当前水位比过去低的话，打开DFR，由于是穆尔型状态机，因此设定状态数目，根据题意可分为六个状态，分别是低于S1，高于S1低于S2同时当前水位比过去高，高于S1低于S2同时当前水位比过去低，高于S2低于S3同时水位比过去低，高于S2低于S3同时水位比过去高，高于S3的水位。

module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
reg [3:0] state,next_state;
reg [3:0] uns1,s1s2norm,s1s2upp,s2s3norm,s2s3upp,aboves3;
// fr3,fr2,fr1,dfr;
assign {fr3,fr2,fr1,dfr}=state;
assign uns1={1’b1,1’b1,1’b1,1’b1};
assign aboves3={1’b0,1’b0,1’b0,1’b0};
assign s1s2norm={1’b0,1’b1,1’b1,1’b0};
assign s1s2upp={1’b0,1’b1,1’b1,1’b1};
assign s2s3norm={1’b0,1’b0,1’b1,1’b0};
assign s2s3upp={1’b0,1’b0,1’b1,1’b1};
always @(posedge clk)
begin
if(reset)
state<=uns1;
else
state<=next_state;
end

always@(*)
begin
case(state)
uns1:
begin
if(s[1]&!s[2]&!s[3])
next_state=s1s2norm;
else
next_state=uns1;
end
s1s2norm:
begin
if(s[1]&s[2]&!s[3])
next_state=s2s3norm;
else if(s[1]&!s[2]&!s[3])
next_state=s1s2norm;
else
next_state=uns1;
end
s1s2upp:
begin
if(s[1]&s[2]&!s[3])
next_state=s2s3norm;
else if(s[1]&!s[2]&!s[3])
next_state=s1s2upp;
else
next_state=uns1;
end
s2s3norm:
begin
if(s[1]&s[2]&s[3])
next_state=aboves3;
else if(s[1]&!s[2]&!s[3])
next_state=s1s2upp;
else
next_state=s2s3norm;
end
s2s3upp:
begin
if(s[1]&s[2]&s[3])
next_state=aboves3;
else if(s[1]&!s[2]&!s[3])
next_state=s1s2upp;
else
next_state=s2s3upp;
end
aboves3:
begin
if(s[1]&s[2]&!s[3])
next_state=s2s3upp;
else
next_state=aboves3;
end
default: next_state=uns1;
endcase
end
endmodule