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RSS订阅原创 奇数分频
3.计数0-(N>>1)周期为高电平，((N>>1)+1)- (N-1)为低电平，占空比大于50%，后续clk_p与clk_n使用与逻辑。计数0-(N>>1)周期为低电平，((N>>1)+1)- (N-1)为低电平，占空比小于50%，后续cl。2.计数N个状态，0-（N-1），if（count == (N-1)） count <= ‘d0;计数N个状态，0-（N-1），if（count == (N-1)） count <= ‘d0;k_p与clk_n使用或逻辑。
2023-06-12 11:41:56
48
原创 round_robin
chnl_a: begin //优先级 chnl_b,chnl_c,chnl_a。chnl_c: begin //优先级 chnl_a,chnl_b,chnl_c。//优先级 chnl_c,chnl_a,chnl_b。
2023-06-09 17:07:05
42
原创 使用matlab生成mif文件
使用matlab生成mif文件用于ROMIP核读取。text文本中一行有5个数据，共有80行，400个1位的数据。地址从左至右，从上至下计，范围为0-399。quartusII的mif文件地址范围从0开始计数，所以如果400个地址，范围是0-399。如果超过399，例如400，就会报错不能打开文件。[data1, data2, data3, data4, data5] = textread('zifu.txt','%n %n %n %n %n');ROM_depth = 400.
2022-05-10 12:05:54
3002
原创 Cs450/gshare
module top_module( input clk, input areset, input predict_valid, input [6:0] predict_pc, output predict_taken, output [6:0] predict_history, input train_valid, input train_taken, input train_mispredicted, input [6:0] train_history, input [6.
2022-03-28 18:26:54
982
原创 Cs450/history shift
module top_module( input clk, input areset, input predict_valid, input predict_taken, output [31:0] predict_history, input train_mispredicted, input train_taken, input [31:0] train_history); always@(posedge clk or p.
2022-03-28 14:50:17
295
原创 Cs450/counter 2bc
module top_module( input clk, input areset, input train_valid, input train_taken, output [1:0] state); reg [1:0] next_state; always@(posedge clk or posedge areset) begin if(areset) state<=2'b01; .
2022-03-28 14:27:09
660
原创 Cs450/timer
module top_module( input clk, input load, input [9:0] data, output tc); reg [9:0] counter; always@(posedge clk) begin if(load) counter<=data; else if(counter!=0) counter<=counter-1'b1; .
2022-03-28 14:01:47
786
原创 HDL Bits Testbenches
Tb/clockmodule top_module ( ); reg clock; dut d(clock); initial clock=0; always #5ps clock=~clock;endmoduleTb/tb1module top_module ( output reg A, output reg B );// // generate input patterns here
2022-03-27 16:03:03
246
原创 HDL Bits Waveform
Sim/circuit1module top_module ( input a, input b, output q );// assign q = a&b; // Fix meendmoduleSim/circuit2module top_module ( input a, input b, input c, input d, output q );// wire sum; as
2022-03-27 15:42:55
205
原创 Finding bugs in code
Bugs mux2module top_module ( input sel, input [7:0] a, input [7:0] b, output [7:0] out); assign out = sel?a:b;endmoduleBugs nand3module top_module (input a, input b, input c, output out);// wire nout; assign out
2022-03-27 14:31:37
223
原创 Exams/review2015 fsmonehot
module top_module( input d, input done_counting, input ack, input [9:0] state, // 10-bit one-hot current state output B3_next, output S_next, output S1_next, output Count_next, output Wait_next, output done, .
2022-03-27 13:56:54
694
原创 Exams/review2015 fancytimer
module top_module ( input clk, input reset, // Synchronous reset input data, output [3:0] count, output counting, output done, input ack ); parameter S0=0,S1=1,S11=2,S110=3,S1101=4,Scounter=5,Sdone=6; reg [2:0.
2022-03-27 13:36:54
99
原创 Exams/review2015 fsm
module top_module ( input clk, input reset, // Synchronous reset input data, output shift_ena, output counting, input done_counting, output done, input ack ); parameter S0=0,S1=1,S11=2,S110=3,S1101=4,Scounter=5,Sd.
2022-03-27 12:02:52
217
原创 Exams/review2015 fsmshift
module top_module ( input clk, input reset, // Synchronous reset output shift_ena); reg [1:0]counter; always@(posedge clk) begin if(reset) begin counter<=0; shift_ena<=1'b1; end .
2022-03-27 11:42:43
196
原创 Exams/review2015 fsmseq
module top_module ( input clk, input reset, // Synchronous reset input data, output start_shifting); parameter S0=0,S1=1,S11=2,S110=3,S1101=4; reg [2:0] state,next_state; always@(posedge clk) begin if(res.
2022-03-27 11:28:16
384
原创 Exams/review2015 shiftcount
module top_module ( input clk, input shift_ena, input count_ena, input data, output [3:0] q); always@(posedge clk) begin if(shift_ena) q<={q[2:0],data}; else if(count_ena) q<=q-1'b.
2022-03-27 11:17:39
279
原创 Exams/review2015 count1k
module top_module ( input clk, input reset, output [9:0] q); always@(posedge clk) begin if(reset) q<=0; else if(q==999) q<=0; else q<=q+1'b1; endendmodul.
2022-03-27 11:11:39
228
原创 Exams/2013 q2bfsm
module top_module ( input clk, input resetn, // active-low synchronous reset input x, input y, output f, output g); parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5,S6=6,S7=7,S8=8; reg [3:0] state,next_state; reg pre_resetn.
2022-03-26 23:29:16
657
原创 Exams/2013 q2afsm
module top_module ( input clk, input resetn, // active-low synchronous reset input [3:1] r, // request output [3:1] g // grant); parameter A=0,B=1,C=2,D=3; reg [1:0] state,next_state; always@(posedge clk) begin .
2022-03-26 23:29:02
406
原创 Fsm3
module top_module( input clk, input in, input areset, output out); // reg [1:0] state,next_state; parameter A=0,B=1,C=2,D=3; // State transition logic always@(*) begin case(state) A: next_state = in?B:.
2022-03-26 23:27:41
275
原创 Conway life
module top_module( input clk, input load, input [255:0] data, output [255:0] q ); integer i; reg [255:0] q_last; reg [17:0] q_a[17:0]; wire [2:0] counter [255:0]; always@(posedge clk) begin if(load) .
2022-03-26 23:26:56
181
原创 Exams/2012 q2b
module top_module ( input [5:0] y, input w, output Y1, output Y3); parameter A=6'b000001,B=6'b000010,C=6'b000100,D=6'b001000,E=6'b010000,F=6'b100000; assign Y1=y[0]&w; assign Y3=(y[1] | y[2] | y[4] | y[5])&(~w);endmo.
2022-03-25 16:48:52
128
原创 Exams/2012 q2fsm
module top_module ( input clk, input reset, // Synchronous active-high reset input w, output z); parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100,F=3'b101; reg [2:0] state,next_state; always@(posedge clk) begin .
2022-03-25 16:44:16
341
原创 Exams/m2014 q6
module top_module ( input clk, input reset, // synchronous reset input w, output z); parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100,F=3'b101; reg [2:0] state,next_state; always@(posedge clk) begin if(r.
2022-03-25 16:39:37
214
原创 Exams/m2014 q6c
module top_module ( input [6:1] y, input w, output Y2, output Y4); parameter A=6'b000001,B=6'b000010,C=6'b000100,D=6'b001000,E=6'b010000,F=6'b100000; assign Y2=(y[1])&&(~w); //assign Y4=(y[2])&&(w) || (y[3].
2022-03-25 16:34:09
581
1
原创 Exams/m2014 q6b
module top_module ( input [3:1] y, input w, output Y2); parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100,F=3'b101; //assign Y2=((y==B)&&(~w)) || ((y==F)&&(~w)) || ((y==B)&&(w)) || ((y==C)&&(w).
2022-03-25 16:22:35
304
原创 Exams/2014 q3c
module top_module ( input clk, input [2:0] y, input x, output Y0, output z); parameter S0=3'b000,S1=3'b001,S2=3'b010,S3=3'b011,S4=3'b100; reg [2:0] next_state; assign Y0=next_state[0]; always@(*) begin .
2022-03-25 16:12:25
425
原创 Exams/2014 q3bfsm
module top_module ( input clk, input reset, // Synchronous reset input x, output z); parameter S0=3'b000,S1=3'b001,S2=3'b010,S3=3'b011,S4=3'b100; reg [2:0] state,next_state; always@(posedge clk) begin if(reset).
2022-03-25 16:06:15
312
原创 Exams/2014 q3fsm
module top_module ( input clk, input reset, // Synchronous reset input s, input w, output z); parameter S0=0,S1=1,S2=2,S3=3; reg [1:0] state,next_state; reg [1:0] counter; always@(posedge clk) begin if(r.
2022-03-25 15:57:45
207
原创 Exams/ece241 2014 q5b
module top_module ( input clk, input areset, input x, output z); parameter S0=0,S1=1; reg state,next_state; always@(posedge clk or posedge areset) begin if(areset) state<=S0; else .
2022-03-25 12:07:32
273
原创 Exams/ece241 2014 q5a
module top_module ( input clk, input areset, input x, output z); parameter S0=0,S1=1,S2=2,S3=3; reg [1:0] state,next_state; always@(posedge clk or posedge areset) begin if(areset) state<=S0; .
2022-03-25 11:56:59
283
原创 Exams/ece241 2013 q8
module top_module ( input clk, input aresetn, // Asynchronous active-low reset input x, output z ); parameter S0=0,S1=1,S2=2; reg [1:0] state,next_state; always@(posedge clk or negedge aresetn) begin if(~arese.
2022-03-22 18:02:36
305
原创 Fsm hdlc
module top_module( input clk, input reset, // Synchronous reset input in, output disc, output flag, output err); parameter S0=0,S1=1,S2=2,S3=3,S4=4,S5=5,S6=6,S7=7; reg [2:0] state,next_state; always@(pos...
2022-03-22 17:26:38
430
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