FPGA基础模块练习（基于牛客刷题）5

LV43 状态机

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
reg [2:0]state,nextstate;
always@(posedge clk or negedge rst)
if(!rst)
state<=3'd0;
else
state<=nextstate;

always@(*)
case(state)
	3'd0:begin nextstate=data?3'd1:3'd0; end
	3'd1:begin nextstate=data?3'd2:3'd1; end
	3'd2:begin nextstate=data?3'd3:3'd2; end
	3'd3:begin nextstate=data?3'd0:3'd3; end
	default: nextstate<=3'd0;
endcase

always@(posedge clk or negedge rst)
if(!rst)
flag<=0;
else if(state==3'd3&&data==1)
flag<=1;
else
flag<=0;

//*************code***********//
endmodule

LV59 根据RTL编写verilog

第一题比较简单，代码如下：

`timescale 1ns/1ns

module RTL(
	input clk,
	input rst_n,
	input data_in,
	output reg data_out
	);

	reg datainregout;
	always@(posedge clk or negedge rst_n)
	if(!rst_n)
		datainregout<=1'd0;
	else
		datainregout<=data_in;

	wire al1out;
	assign al1out=data_in&(~datainregout);

	always@(posedge clk or negedge rst_n)
	if(!rst_n)
		data_out<=0;
	else
		data_out<=al1out;


	

endmodule

VL60 使用握手信号实现跨时钟域数据传输

先按照逻辑写driver模块