[内核移植]内核移植过程

内核移植

本次移植的开发板是基于 imx6ull 的 linux 开发板,开发板名称为 igkboard,因此之后的许多文件都会以此命名,本次移植的内核版本为 lf-5.15.32-2.0.0

1 安装软件包

一般情况下,编译内核前需要使用如下命令安装软件包

sudo apt-get install lzop
sudo apt-get install libncurses5-dev
sudo apt-get install libssl-dev

2 修改顶层 Makefile

2.1 修改默认架构和默认交叉编译器

在编译内核时,我们使用的一般命令步骤是,先清除构建,然后配置内核,最后执行编译,操作步骤如下
注:最后一行命令,-j 用于指定编译所使用的线程数,如果服务器分配有 n 个核,则 -j 后的参数为 2*n

make ARCH=arm CROSS_COMPILE=/opt/buildroot/cortexA7/bin/arm-linux- distclean
make ARCH=arm CROSS_COMPILE=/opt/buildroot/cortexA7/bin/arm-linux- xxx_defconfig
make ARCH=arm CROSS_COMPILE=/opt/buildroot/cortexA7/bin/arm-linux- -j16

为简化操作我们可以在顶层 Makefile 进行设置,要修改的内容就是目标架构和交叉编译器,在顶层 Makefile 中找到 ARCH 和 CROSS_COMPILE 然后进行如下修改

ARCH = arm
CROSS_COMPILE ?= /opt/buildroot/cortexA7/bin/arm-linux-

这样在我们进行内核编译时,就不需要每次都设定 ARCH 和 CROSS_COMPILE,直接使用如下命令即可

make distclean
make xxx_defconfig
make -j16

2.2 添加 dtbo 的编译支持

-o -name '*.ko.*' \
-o -name '*.dtb' -o -name '*.dtbo' -o -name '*.dtb.S' -o -name '*.dt.yaml' \
-o -name '*.dtbo' \
-o -name '*.dwo' -o -name '*.lst' \
-o -name '*.su' -o -name '*.mod' \

3 修改设备树并添加 dt overlays 设备树文件

3.1 为开发板添加自己的设备树文件

打开 /arch/arm/boot/dts 添加 igkboard 自己的设备树文件 igkboard.dts 这个设备树文件需要对 imx6ull-14x14-evk-emmc.dts 以及其包含的头文件 dtsi 进行归总,并添加自己需要的设备的设备树信息,笔者总结的设备树文件如下

/*
 * Device Tree Source for LingYun IGKBoard(IoT Gateway Kit Board)
 * Based on imx6ul-14x14-evk.dts/imx6ul-14x14-evk.dtsi
 *
 * Copyright (C) 2022 LingYun IoT System Studio.
 * Author: Linke<731253265@qq.com>
 */

/dts-v1/;

#include "imx6ull.dtsi"

/ {
    model = "LingYun IoT System Studio IoT Gateway Board";
	compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";

	chosen {
		stdout-path = &uart1;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x20000000>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0xa000000>;
			linux,cma-default;
		};
	};

	mq2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "my_mq2";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mq2>;
		mq2-gpio = <&gpio5 1 GPIO_ACTIVE_LOW>;
		interrupt-parent = <&gpio5>;
		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
		status = "okay";
	};

	buzzer: pwm-buzzer {
		compatible = "pwm-beeper";
		pwms = <&pwm2 0 500000>;
		status = "okay";
	};

	pxp_v4l2 {
		compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
		status = "okay";
	};

	reg_sd1_vmmc: regulator-sd1-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
		off-on-delay-us = <20000>;
		enable-active-high;
	};

	reg_peri_3v3: regulator-peri-3v3 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_peri_3v3>;
		regulator-name = "VPERI_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
		/*
		 * If you want to want to make this dynamic please
		 * check schematics and test all affected peripherals:
		 *
		 * - sensors
		 * - ethernet phy
		 * - can
		 * - bluetooth
		 * - wm8960 audio codec
		 * - ov5640 camera
		 */
		regulator-always-on;
	};

	reg_can_3v3: regulator-can-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "can-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_vref_adc: regulator@2 {
		compatible = "regulator-fixed";
		regulator-name = "VREF_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

/*+--------------+
  | Misc Modules |
  +--------------+*/

&snvs_poweroff {
	status = "okay";
};

&snvs_pwrkey {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&pwm2 { 
	#pwm-cells = <2>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "okay";
};

/*+-------------------+
  | i2c Device Module |
  +-------------------+*/

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

/*+-------------------+
  | iio Device Module |
  +-------------------+*/

&adc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc1>;
	num-channels = <2>;
	vref-supply = <&reg_vref_adc>;
	status = "okay";
};

/*+---------------+
  | Camera Module |
  +---------------+*/

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	ov5640: ov5640@3c {
		compatible = "ovti,ov5640";
		reg = <0x3c>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_csi1 &pinctrl_camera_clock>;
		clocks = <&clks IMX6UL_CLK_CSI>;
		clock-names = "csi_mclk";
		csi_id = <0>;
		mclk = <24000000>;
		mclk_source = <0>;
		status = "disabled";
		port {
			ov5640_ep: endpoint {
				remote-endpoint = <&csi1_ep>;
			};
		};
	};

};

&csi {
	status = "disabled";

	port {
		csi1_ep: endpoint {
			remote-endpoint = <&ov5640_ep>;
		};
	};
};

/*+--------------+
  | Audio Module |
  +--------------+*/

&clks {
	assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
	assigned-clock-rates = <786432000>;
};

/*+------------------+
  | Ethernet Modules |
  +------------------+*/

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet1>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	phy-supply = <&reg_peri_3v3>;
	status = "okay";
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet2>;
	phy-mode = "rmii";
	phy-handle = <&ethphy1>;
	phy-supply = <&reg_peri_3v3>;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-id0022.1560";
			reg = <0>;
			micrel,led-mode = <1>;
			clocks = <&clks IMX6UL_CLK_ENET_REF>;
			clock-names = "rmii-ref";

		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-id0022.1560";
			reg = <1>;
			micrel,led-mode = <1>;
			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
			clock-names = "rmii-ref";
		};
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can_3v3>;
	status = "okay";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can_3v3>;
	status = "okay";
};

/*+---------------+
  | USB interface |
  +---------------+*/

&usbotg1 {
	dr_mode = "otg";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb_otg1>;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	status = "okay";
};

&usbphy1 {
	fsl,tx-d-cal = <106>;
};

&usbphy2 {
	fsl,tx-d-cal = <106>;
};

/*+------------------+
  | USDCHC interface |
  +------------------+*/

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
	keep-power-in-suspend;
	wakeup-source;
	vmmc-supply = <&reg_sd1_vmmc>;
	status = "okay";
};

&usdhc2 {
    pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2_8bit>;
	pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
    non-removable;
	bus-width = <8>;
    keep-power-in-suspend;
	wakeup-source;
	status = "okay";
};

/*+----------------------+
  | Basic pinctrl iomuxc |
  +----------------------+*/

&iomuxc {
	pinctrl-names = "default";

	pinctrl_camera_clock: cameraclockgrp {
		fsl,pins = <
			MX6UL_PAD_CSI_MCLK__CSI_MCLK		0x1b088
		>;
	};

	pinctrl_csi1: csi1grp {
		fsl,pins = <
			MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK	0x1b088
			MX6UL_PAD_CSI_VSYNC__CSI_VSYNC		0x1b088
			MX6UL_PAD_CSI_HSYNC__CSI_HSYNC		0x1b088
			MX6UL_PAD_CSI_DATA00__CSI_DATA02	0x1b088
			MX6UL_PAD_CSI_DATA01__CSI_DATA03	0x1b088
			MX6UL_PAD_CSI_DATA02__CSI_DATA04	0x1b088
			MX6UL_PAD_CSI_DATA03__CSI_DATA05	0x1b088
			MX6UL_PAD_CSI_DATA04__CSI_DATA06	0x1b088
			MX6UL_PAD_CSI_DATA05__CSI_DATA07	0x1b088
			MX6UL_PAD_CSI_DATA06__CSI_DATA08	0x1b088
			MX6UL_PAD_CSI_DATA07__CSI_DATA09	0x1b088
		>;
	};

	pinctrl_enet1: enet1grp {
		fsl,pins = <
			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
		>;
	};

	pinctrl_enet2: enet2grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
			MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
			MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2	0x4001b031
		>;
	};

	pinctrl_flexcan1: flexcan1grp{
		fsl,pins = <
			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
		>;
	};

	pinctrl_flexcan2: flexcan2grp{
		fsl,pins = <
			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO02__I2C1_SCL	0x4001b8b0
			MX6UL_PAD_GPIO1_IO03__I2C1_SDA	0x4001b8b0
		>;
	};	

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
		>;
	};

	pinctrl_lcdif_dat: lcdifdatgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
			MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
			MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
			MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
			MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
			MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
			MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
		>;
	};

	pinctrl_lcdif_ctrl: lcdifctrlgrp {
		fsl,pins = <
			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
			/* used for lcd reset */
			MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
		>;
	};

	pinctrl_peri_3v3: peri3v3grp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02	0x1b0b0
		>;
	};

	pinctrl_pwm1: pwm1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO08__PWM1_OUT			0x110b0 
		>;
	};

	pinctrl_pwm7: pwm7grp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TCK__PWM7_OUT	0x110b0
		>;
	};

	pinctrl_pwm8_nbiot: pwm8nbiotgrp {
		fsl,pins = <
			MX6UL_PAD_JTAG_TRST_B__PWM8_OUT	0x110b0
		>;
	};

	pinctrl_spi4: spi4grp {
		fsl,pins = <
			MX6UL_PAD_BOOT_MODE0__GPIO5_IO10	0x70a1
			MX6UL_PAD_BOOT_MODE1__GPIO5_IO11	0x70a1
			MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07	0x70a1
			MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08	0x80000000
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
		>;
	};

	pinctrl_usb_otg1: usbotg1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID	0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     	0x17059
			MX6UL_PAD_SD1_CLK__USDHC1_CLK		0x10071
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 	0x17059
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 	0x17059
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 	0x17059
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 	0x17059
			MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 
			MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 
			MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9

		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
		>;
	};

	pinctrl_usdhc2_8bit: usdhc2grp_8bit {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x10069
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
		>;
	};

	pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100b9
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170b9
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
		>;
	};

	pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
		fsl,pins = <
			MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x100f9
			MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x170f9
			MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
			MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
			MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
			MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
			MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
			MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
			MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
			MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
		>;
	};

	pinctrl_spi_uart8: spi_uart8_grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK	0x10b0
			MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	0x10b0
			MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	0x10b0
			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	0x10b0
		>;
	};	

	pinctrl_mq2: mq2_grp {
		fsl,pins = <
			MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x110b0
		>;
	};

	pinctrl_adc1: adc1grp {
		fsl,pins = <
			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
		>;
	};
};

3.2 添加 dt overlays 设备树文件

在 /arch/arm/boot/dts 下添加 overlays 文件夹,在这个文件夹下的添加 dt overlays 的 dts 文件,我们会在之后对其 Makefile 进行修改,并将其编译成 dtbo 文件,会将这些文件放在 emmc 中,并使用 uboot 命令使用设备树覆盖机制,动态改变管脚规则,所添加的 dt overlays 文件在此只展示部分示例,示例是为 igkboard.dtb 添加了一个 spi 协议的 oled 屏的设备树信息,之后想要使用该 oled 可以在 uboot 中使用命令打补丁

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include "../imx6ul-pinfunc.h"

&ecspi1 {
	fsl,spi-num-chipselects = <1>;
	cs-gpio = <&gpio3 26 GPIO_ACTIVE_LOW>;
    reset-gpio = <&gpio5 1 GPIO_ACTIVE_LOW>;
 	dc-gpio = <&gpio5 8 GPIO_ACTIVE_LOW>;
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_spi_uart8
                 &pinctrl_oled_reset
                 &pinctrl_oled_dc>;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;

	spidev0: oled_spi@0 {
		reg = <0>;
		compatible = "oled_spi";
		spi-max-frequency = <8000000>;
	};	
};

&iomuxc {
	pinctrl_spi_uart8: spi_uart8_grp {
		fsl,pins = <
			MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK       0x10b0
			MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI	    0x10b0
			MX6UL_PAD_LCD_DATA23__ECSPI1_MISO	    0x10b0
			MX6UL_PAD_LCD_DATA21__GPIO3_IO26	    0x10b0
		>;
	};	

    pinctrl_oled_reset: oled_reset_grp {
    	fsl,pins = <
    		MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01	    0x10B0
    	>;
    };
        
    pinctrl_oled_dc: oled_dc_grp {
    	fsl,pins = <
    		MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x10B0
    	>;
    };
};

4 修改设备树相关的 Makefile

打开 /arch/arm/boot/dts 文件夹下的 Makefile 添加如下内容,用于在编译内核时,对 igkboard.dts 进行编译,其中 DTC_FLAGS_igkboard := -@,是因为只有在编译中添加了 -@,编译后的 dts 文件才能打上 dt overlays 的补丁文件 dtbo,并添加子文件目录,也就是编译时执行 overlays 文件夹下的 Makefile 从而 dt overlays 设备树文件编译成 dtbo

DTC_FLAGS_igkboard := -@
dtb-$(CONFIG_SOC_IMX6UL) += igkboard.dtb
subdir-$(CONFIG_SOC_IMX6UL) += overlays

然后,在 /arch/arm/boot/dts/overlays 文件夹中添加 Makefile 文件,并添加如下内容,用于将该文件下的所有 dts 文件都编译成 dtbo 文件,作为备用,给 igkboard.dtb 打补丁

# SPDX-License-Identifier: GPL-2.0

# required for overlay support
DTC_FLAGS += -@

dtb-y += can1.dtbo
dtb-y += can2.dtbo
dtb-y += i2c1.dtbo
dtb-y += spi1.dtbo
dtb-y += uart2.dtbo
dtb-y += uart3.dtbo
dtb-y += uart4.dtbo
dtb-y += uart7.dtbo
dtb-y += pwm7.dtbo
dtb-y += pwm8.dtbo
dtb-y += w1.dtbo
dtb-y += lcd.dtbo
dtb-y += cam.dtbo
dtb-y += nbiot-4g.dtbo

5 添加 igkboard 的 defconfig 文件

直接将 imx_v7_defconfig 复制一份,并修改名字为 igkboard_defconfig 即可

6 编译内核

使用之前提到的命令编译内核

make distclean
make igkboard_defconfig
make -j16

编译完成后我们可以在内核源码文件夹下看到 vmlinux 以及 /arch/arm/boot 文件夹下看到 Image 和 zImage 文件
对于内核文件,vmlinux 就是最原始的内核文件,但是该文件太大,不利于传输,因此对其进行压缩,这个过程是,先利用 objcopy 取消掉 vmlinux 中的一些信息,比如符号之类的,然后生成 Image 文件,然后用 gzip 工具,对 Image 文件进行压缩,最后生成 zImage 文件,然后将 zImage 烧录到开发板即可
最后,在移植完内核之后,最重要的是要对移植后的内核进行测试,这一部分内容之后再做总结

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