- 博客(10)
- 收藏
- 关注
RSS订阅原创 Exams/2014 q3bfsm
Given the state-assigned table shown below, implement the finite-state machine. Reset should reset the FSM to state 000.module top_module ( input clk, input reset, // Synchronous reset input x, output z); reg [2:0] state;
2022-01-19 14:37:31
358
原创 HDLBits刷题之：Lemmings1-3
Lemmings1：The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine.In the Lemmings’ 2D world, Lemmings can be in one of two states: walking left or walking right. It will switch d
2022-01-17 21:06:13
783
原创 Fsm3 See also: State transition logic for this FSM
The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.下面是一输入一输出四状态的摩尔状态机的状态转移表。实现这个状态机。包括将 FSM 重置为状态 A
2022-01-16 17:01:09
380
原创 Fsm serialdata
See also: Serial receiverNow that you have a finite state machine that can identify when bytes are correctly received in a serial bitstream, add a datapath that will output the correctly-received data byte. out_byte needs to be valid when done is 1, and i
2022-01-15 10:53:44
177
原创 Fsm serial
In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The l
2022-01-14 15:03:32
223
原创 【无标题】
Implement a Mealy-type finite state machine that recognizes the sequence “101” on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the “101” sequence is detected. Your FSM should also have an active-low as
2022-01-13 19:12:01
133
原创 Taken from 2015 midterm question 5. See also the first part of this question: mt2015_muxdff
Write the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named top_module). Assume that you are going to implement the circuit on the DE1-SoC board. Connect the R inputs to the SW switches, connect Clock to KEY[0], a
2022-01-12 14:46:27
549
原创 2021-10-14
关于FPGA时钟二分频输出的简单实现clock_dive文件，这里通过计数器来计算基准时钟clkmodule clock_dive( //时钟分频器 clk, clk1, rst_n);input clk;input rst_n;output clk1;reg cnt;wire add_cnt;wire end_cnt;wire clk;reg clk1;wire rst_n;always @(posedge clk or negedge r
2021-10-14 21:47:16
85
原创 python turtle画心型
import turtleclass heart(turtle.Turtle):def draw_heart(self):self.begin_fill()self.goto(-100,100)self.left(135)self.circle(-59,220)self.penup()self.home()self.pendown()self.goto(100,100)s...
2020-02-14 18:42:28
334
空空如也
空空如也
TA创建的收藏夹 TA关注的收藏夹
TA关注的人