Exams/2014 q3bfsm

Given the state-assigned table shown below, implement the finite-state machine. Reset should reset the FSM to state 000.

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);
    
    reg [2:0] state;
    reg [2:0] next_state;
    
    parameter S0=3'b000;
    parameter S1=3'b001;
    parameter S2=3'b010;
    parameter S3=3'b011;
    parameter S4=3'b100;
    
    always @(posedge clk) begin
        if (reset==1) 
            state<=S0;
        else 
           state<=next_state;
    end
  
    always @(*) begin
        case (state) 
            S0: if (x==0)
				next_state=S0;
            	else 
                next_state=S1;
            S1: if (x==0)
				next_state=S1;
            	else 
                next_state=S4;
            S2: if (x==0)
				next_state=S2;
            	else 
                next_state=S1;
            S3: if (x==0)
				next_state=S1;
            	else 
                next_state=S2;
            S4: if (x==0)
				next_state=S3;
            	else 
                next_state=S4;
            default : next_state=S0;
        endcase
    end
    
    always @(posedge clk) begin
        if (reset==1) 
            z<=0;
        else case (next_state) 
            S0:z<=0;
             S1:z<=0;
             S2:z<=0;
             S3:z<=1;
             S4:z<=1;
          
        endcase
        
    end
    
    endmodule