This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.
This exercise is the same as fsm2s, but using asynchronous reset.
使用三段式状态机完成
module top_module(
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out); //
parameter OFF=0, ON=1;
reg state, next_state;
always @(posedge clk, posedge areset) begin
if (areset==1) begin
state<=OFF;
end
else
state<=next_state;
end
always @(*) begin
if (areset==1)
next_state<=OFF;
else case(state)
OFF: if (j==1)
next_state<=ON;
else
next_state<=OFF;
ON: if (k==1)
next_state<=OFF;
else
next_state<=ON;
endcase
end
always @(posedge clk, posedge areset) begin
if(areset==1 )
out<=0;
else case (next_state)
OFF:out<=0;
ON:out<=1;
endcase
end
endmodule