Modelsim 10.7安装遇到的问题

下载modelsim安装后,用crack破解失败显示找不到mgls.dll,运行破解所用的patch_dll.bat成功并生成license,之后系统变量设置也米问题,直到

点击modelsim图标时弹出了这个!!!

 

 

网上一堆方法用了也没有解决,最后找到一个方法,瞎搞一通给解决了,记录一下方法,免得忘记。

编辑patch_dll.bat文件,添加标红两条语句

@echo off
attrib -r mgls.dll
attrib -r mgls64.dll
MentorKG.exe -patch . 
attrib +r mgls.dll
attrib +r mgls64.dll

同时将mgls.dll命名改成mgls64.dll,推测我的问题是按64位破解的,但是mgls.dll文件名没有加“64”所以找不到(crack破解失败估计也是这个原因)。

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下面是原博主的链接,大家可以参考着看看。希望可以帮到大家

原文链接:https://blog.csdn.net/qq_39254662/article/details/109552319

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Mentor, a Siemens business, has unveiled ModelSim 10.7, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment. About Mentor Graphics ModelSim. Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused. In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code. The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).
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