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原创 Linux下为空白SD卡建立BOOT，rootfs分区

Linux下为空白SD卡建立BOOT，rootfs分区准备VMware workstationsubuntu 20.0.2SD卡（16GB）安装工具gpartedsudo apt-get install gparted分区1.启动工具sudo gparted2.选中需要分区的SD卡如果存在默认分区先右击分区，点击unmount，再选择delete。3.右击unallocated分区->NewBOOT分区设置为fat32格式，大小自己设置，我设置了8G，Free spac

2022-04-29 16:07:38 1092

原创 HDLBits Design a Moore FSM Examsece241 2013 q4

HDLBits Design a Moore FSM Exams/ece241 2013 q4网址：https://hdlbits.01xz.net/wiki/Exams/ece241_2013_q4题目大意是设计一个记录水位的状态机，可以设计六个状态表示表格中的water level，其中Between s3 and s2与between s2 and s3分别用两个表示上升至该水位或下降至该水位，Above S3和Below S1用两个状态表示。module top_module ( in

2022-04-05 21:10:14 342

原创 Linux下Vivado安装流程

Linux下Vivado安装流程1.下载在官网（www.xilinx.com）下载想要版本的标准免费版，以20.3为例。（下载这玩意还要注册一个账号，填一些东西，不过一劳永逸）把.bin文件下载到自己喜欢的目录下执行：cd 喜欢的目录chmod a+x Xilinx_Unified_2020.3_0407_2214_Lin64.bin./Xilinx_Unified_2020.3_0407_2214_Lin64.bin之后会出现安装界面。2.安装安装前会询问是否更新到最新版，选con

2022-03-29 20:48:11 11458 6

原创牛客网Verilog进阶——VL13 时钟分频（偶数）

牛客网Verilog进阶——VL13 时钟分频（偶数）描述请使用D触发器设计一个同时输出2/4/8分频的50%占空比的时钟分频器注意rst为低电平复位`timescale 1ns/1nsmodule even_div ( input wire rst , input wire clk_in, output reg clk_out2, output reg clk_out4, output reg clk_out8

2022-03-25 22:32:08 195

原创 HDLBits PS2

HDLBits PS/2Fsm ps2网址：https://hdlbits.01xz.net/wiki/Fsm_ps2The PS/2 mouse protocol sends messages that are three bytes long. However, within a continuous byte stream, it’s not obvious where messages start and end. The only indication is that the first b

2022-03-23 16:19:04 229

原创 HDLBits Lemmings1-4

HDLBits Lemmings1-4Lemming1网址：https://hdlbits.01xz.net/wiki/Lemmings1The game Lemmings involves critters with fairly simple brains. So simple that we are going to model it using a finite state machine.In the Lemmings’ 2D world, Lemmings can be in one o

2022-03-22 22:02:34 358

原创 HDLbits Count clock

HDLbits Count clockCreate a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).reset resets the clo

2022-03-17 16:32:49 542

原创 HDLBits Countbcd

HDLBits Countbcd网址：https://hdlbits.01xz.net/wiki/CountbcdBuild a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable sign

2022-03-16 19:29:39 180

原创 HDLBits Edgecapture

Edgecapture网址：https://hdlbits.01xz.net/wiki/EdgecaptureFor each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. “Capture” means that the output will remain 1 until the register is reset (synchronous

2022-03-15 11:31:06 422

原创 HDLBits Examsece241 2014 q5a

HDLBits Exams/ece241 2014 q5a1.题目题目链接：https://hdlbits.01xz.net/wiki/Exams/ece241_2014_q5a You are to design a one-input one-output serial 2’s complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the

2021-12-01 21:29:04 1073

原创 HDLBits FSMHDLC

HDLBits FSMHDLC1.题目 {#1题目}Synchronous HDLC framing involves decoding a continuous bit stream of data to look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a “flag” that indic

2021-12-01 18:33:08 330

原创 modelsim64位破解版安装mgls.dll文件找不到解决方法

下载modelsim，安装后运行破解所用的patch_dll.bat发生闪退，闪过的界面显示找不到mgls.dll文件，此时需要右键编辑patch_dll.bat文件为@echo offattrib -r mgls.dllattrib -r mgls64.dllMentorKG.exe -patch .attrib +r mgls.dllattrib +r mgls64.dll保存后再次运行即可产生LICENSE.TXT文件。...

2021-11-30 17:08:04 6065 7

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