MODELSIM软件安装及基础

Verilog第一节 软件安装及半导体基础

仅自用学习参考。

ModelSim

安装包:链接:https://pan.baidu.com/s/1oqMujqJnRVGG8ZV5T1d3qQ?pwd=sqdm
提取码:sqdm
安装步骤:
1 先将modelsim解压,再将modelsim中压缩子文件夹Crack解压

2 点击modelsim-win64-10.7-se.exe
点击modelsim-win64-10.7-se.exe

3 加载完成后,点击下一步
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4 将软件放置与C盘或者其他盘,我C盘很大,就直接点下一步了(点是)
重点:安装路径要记住,等会儿要用
在这里插入图片描述
5 协议点同意,进入安装界面
在这里插入图片描述
6 安装期间会有三次弹窗,直接点是

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Mentor, a Siemens business, has unveiled ModelSim 10.7, is unified debug and simulation environment gives today's FPGA designers advanced capabilities in a productive work environment. About Mentor Graphics ModelSim. Modelsim HDL simulator provides FPGA customers with and easy cost-effective way to speed up FPGA development, lab bring up and test. Many FPGA designers go to the lab before adequately vetting their design. This means weeks or even months of inefficient debugging time in the lab. Testing in the lab has limited visibility of the signals in design. It can take 8 hours to do a place and route just instrument additional signals or make a small bug fix. With simulation the debug loop is much faster and there is complete visibility into the signals in the design. Simulation enables a much higher quality FPGA design before entering the lab allowing time spent during lab debug much more productive and focused. In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code. The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).
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