MSP430 ADC12（一）

以下代码运行ADC12模块，P6.0为输入通道，P1.0为输出。当输入电压大于0.5电源电压VCC时点亮LED。
注意：__even_in_range(ADC12IV,34) 是判断ADC12IV是否为0-34之间的偶数，如果是执行switch语句，此做法是为了提高switch语句的执行效率，用于多中断来源判断。

#include <msp430.h>

int main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  ADC12CTL0 = ADC12SHT02 + ADC12ON;         // 采样时间,打开ADC12
  ADC12CTL1 = ADC12SHP;                     // 使用采样定时器
  ADC12IE = 0x01;                           // 0通道中断使能
  ADC12CTL0 |= ADC12ENC;                    // ADC12使能
  P6SEL |= 0x01;                            // P6.0选择ADC通道
  P1DIR |= 0x01;                            // P1.0输出

  while (1)
  {
    ADC12CTL0 |= ADC12SC;                   // 开始采样转换
    
    __bis_SR_register(LPM0_bits + GIE);     // LPM0, ADC12_ISR强制退出
    __no_operation();                       // For debugger
  }
}

#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector = ADC12_VECTOR
__interrupt void ADC12_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(ADC12_VECTOR))) ADC12_ISR (void)
#else
#error Compiler not supported!
#endif
{
  switch(__even_in_range(ADC12IV,34))
  {
  case  0: break;                           // Vector  0:  No interrupt
  case  2: break;                           // Vector  2:  ADC overflow
  case  4: break;                           // Vector  4:  ADC timing overflow
  case  6:                                  // Vector  6:  ADC12IFG0
    if (ADC12MEM0 >= 0x7ff)                 // ADC12MEM = A0 > 0.5AVcc?
      P1OUT |= BIT0;                        // P1.0 = 1
    else
      P1OUT &= ~BIT0;                       // P1.0 = 0

    __bic_SR_register_on_exit(LPM0_bits);   // Exit active CPU
  case  8: break;                           // Vector  8:  ADC12IFG1
  case 10: break;                           // Vector 10:  ADC12IFG2
  case 12: break;                           // Vector 12:  ADC12IFG3
  case 14: break;                           // Vector 14:  ADC12IFG4
  case 16: break;                           // Vector 16:  ADC12IFG5
  case 18: break;                           // Vector 18:  ADC12IFG6
  case 20: break;                           // Vector 20:  ADC12IFG7
  case 22: break;                           // Vector 22:  ADC12IFG8
  case 24: break;                           // Vector 24:  ADC12IFG9
  case 26: break;                           // Vector 26:  ADC12IFG10
  case 28: break;                           // Vector 28:  ADC12IFG11
  case 30: break;                           // Vector 30:  ADC12IFG12
  case 32: break;                           // Vector 32:  ADC12IFG13
  case 34: break;                           // Vector 34:  ADC12IFG14
  default: break; 
  }
}