一位全减器VHDL语言

一位全减器VHDL语言描述

LIBRARY IEEE;                     
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY h_subtractor IS
  PORT(a,b:IN STD_LOGIC;
       co,so:OUT STD_LOGIC);
END ENTITY h_subtractor;
ARCHITECTURE fh1 OF h_subtractor IS
BEGIN 
   so<=a XOR b;
	co<=(NOT a) AND b;
END ARCHITECTURE fh1;

LIBRARY IEEE;         
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY f_subtractor IS
  PORT (y,x,sub_in:IN STD_LOGIC;
      diff,sub_out:OUT STD_LOGIC);
END ENTITY f_subtractor;
ARCHITECTURE fd1 OF f_subtractor IS 
     COMPONENT h_subtractor
	    PORT (a,b:IN STD_LOGIC;
		       co,so:OUT STD_LOGIC);
	  END COMPONENT;
	  SIGNAL d,e:STD_LOGIC;
BEGIN
     u1: h_subtractor PORT MAP(a=>y,b=>x,co=>d,so=>e);
	 u2: h_subtractor PORT MAP(a=>e,b=>sub_in,so=>diff);
	 sub_out<=((NOT y) AND sub_in) OR ((NOT y)AND x AND (NOT sub_in)) OR (y AND x AND sub_in);
END ARCHITECTURE fd1;