2021-08-13

verilog输出有规律的数

0,8,2,10,4,12,6,14; 1,9,3,11,5,13,7,15
16,
32,
48,
64,
设计计数器
cnt0 计2
cnt1 计4
cnt2 计2
cnt3 计5
addr=cnt08+cnt12+cnt2+cnt3*16；

module addr_gen(clk,rst_n,addr);
input clk;
input rst_n;
output addr;

reg  [6:0] addr;
reg cnt0; wire add_cnt0; wire end_cnt0;//计2
reg [1:0] cnt1; wire add_cnt1; wire end_cnt1;//计4
reg cnt2; wire add_cnt2; wire end_cnt2;//计2
reg [2:0] cnt3; wire add_cnt3; wire end_cnt3;//计5

always @ (posedge clk or negedge rst_n) begin
 if  (!rst_n) begin
  addr<=0;
 end
 else if (!end_cnt3) begin
  addr<=cnt0*8+cnt1*2+cnt2*1+cnt3*16;
 end
 else begin
  addr<=0;
 end
end

always @ (posedge clk or negedge rst_n) begin
 if  (!rst_n) begin
  cnt0<=0;
 end
 else if (add_cnt0) begin
  if (end_cnt0) 
   cnt0<=0;
  else
   cnt0<=cnt0+1;
 end
end
assign add_cnt0=1;
assign end_cnt0=add_cnt0 && (cnt0==2-1);

always @ (posedge clk or negedge rst_n) begin
 if  (!rst_n) begin
  cnt1<=0;
 end
 else if (add_cnt1) begin
  if (end_cnt1) 
   cnt1<=0;
  else
   cnt1<=cnt1+1;
 end
end
assign add_cnt1=end_cnt0;
assign end_cnt1=add_cnt1&&(cnt1==4-1);

always @ (posedge clk or negedge rst_n) begin
 if  (!rst_n) begin
  cnt2<=0;
 end
 else if (add_cnt2) begin
  if (end_cnt2) 
   cnt2<=0;
  else
   cnt2<=cnt2+1;
 end
end
assign add_cnt2=end_cnt1;
assign end_cnt2=add_cnt2&&(cnt2==2-1);//0

always @ (posedge clk or negedge rst_n) begin
 if  (!rst_n) begin
  cnt3<=0;
 end
 else if (add_cnt3) begin
  if (end_cnt3) 
   cnt3<=0;
  else
   cnt3<=cnt3+1;
 end
end
assign add_cnt3=end_cnt2;
assign end_cnt3=add_cnt3&&(cnt3==5-1);

endmodule

结果：（16进制的addr）