前文中,我们介绍了毛刺的一种解决方案。此毛刺是通过两个信号的与造成的,可以通过打拍子解决。笔者最近遇到了一个由于硬件电路产生的问题,通过打拍子无法解决,于是可以通过计数器来过滤掉毛刺。具体的操作方式如下:
reg [3:0]io1;
reg [7:0]cnt1,cnt2,cnt3,cnt4;
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
io1[0] <= 1'b1;
cnt1 <= 8'b0;
end
else
begin
if(cnt1 < 8'd4 && (io[0] == 1'b1 ) )
cnt1 <= cnt1 +1'b1;
else if(cnt1 == 8'd4 )
begin
cnt1 <= 8'd0;
io1[0] <= 1'b1;
end
else if((io[0] == 1'b0))
begin
cnt1 <= 8'b0;
io1[0] <= 1'b0;
end
end
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
io1[1] <= 1'b1;
cnt2 <= 8'b0;
end
else
begin
if(cnt2 < 8'd4 && (io[1] == 1'b1 ) )
cnt2 <= cnt2 +1'b1;
else if(cnt2 == 8'd4 )
begin
cnt2 <= 8'd0;
io1[1] <= 1'b1;
end
else if((io[1] == 1'b0))
begin
cnt2 <= 8'b0;
io1[1] <= 1'b0;
end
end
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
io1[2] <= 1'b1;
cnt3 <= 8'b0;
end
else
begin
if(cnt3 < 8'd4 && (io[2] == 1'b1 ) )
cnt3 <= cnt3 +1'b1;
else if(cnt3 == 8'd4 )
begin
cnt3 <= 8'd0;
io1[2] <= 1'b1;
end
else if((io[2] == 1'b0))
begin
cnt3 <= 8'b0;
io1[2] <= 1'b0;
end
end
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
io1[3] <= 1'b1;
cnt4 <= 8'b0;
end
else
begin
if(cnt4 < 8'd4 && (io[3] == 1'b1 ) )
cnt4 <= cnt4 +1'b1;
else if(cnt4 == 8'd4 )
begin
cnt4 <= 8'd0;
io1[3] <= 1'b1;
end
else if((io[3] == 1'b0))
begin
cnt4 <= 8'b0;
io1[3] <= 1'b0;
end
end
此io口是外出高电平触发的接入,给于io[0]高电平的同时,会对io[1],io[2],io[3],产生一个发生时间不可知的毛刺,可以通过计数器解决~
笔者一开始想通过一个always语句来解决及
...
if(cnt <= 8'd4 &&(io[0] == 1'b1 | io[1] == 1'b1 | io[2] == 1'b1 | io[3] == 1'b1))
..
但是效果并不好,但是因为verilog是并行语言,所以分开写效果也是一样~