操作系统复习六

Background:
Program must be brought (from disk) into memory and
placed within a process for it to be run
◼ Main memory and registers are only storage CPU can
access directly
◼ Memory unit only sees a stream of addresses + read
requests, or address + data and write requests
◼ Register access in one CPU clock (or less)
◼ Main memory can take many cycles, causing a stall
◼ Cache sits between main memory and CPU registers
◼ Protection of memory required to ensure correct operation

From Program To Process

Base and Limit Registers:
◼ A pair of base and limit registers
define the logical address space 一对基数和极限寄存器 定义逻辑地址空间
◼ CPU must check every memory
access generated in user mode to
be sure it is between base and limit
for that user CPU必须检查每一个在用户模式下产生的内存访问的 访问，以确保它在基数和极限之间。 确定它是在基数和极限之间。
◼ Base register contains value of
smallest physical address 基准寄存器包含最小物理地址的值
◼ Limit register contains range of
logical addresses – each logical
address must be less than the limit
register 限制寄存器包含逻辑地址的范围 逻辑地址范围 - 每个逻辑 地址必须小于极限 寄存器

Address Binding
◼ Programs on disk, ready to be brought into memory to execute form
an input queue磁盘上的程序，准备带入内存执行，形成一个输入队列
⚫Without support, must be loaded into address 0000
如果没有支持，必须载入地址0000
◼ Inconvenient to have first user process physical address always at 0000
不方便让第一个用户进程的物理地址总是在0000。
◼ Further, addresses represented in different ways at different stages of a program’s life
此外，在程序的不同阶段，地址以不同的方式表示。
⚫ Source code addresses usually symbolic
源代码地址通常是符号性的
⚫ Compiled code addresses bind to relocatable addresses  i.e. “14 bytes from beginning of this module”
编译后的代码地址与可重定位的地址绑定，即 “从本模块开始的14字节”。

⚫ Linker or loader will bind relocatable addresses to absolute addresses  i.e. 74014
链接器或加载器将把可重定位的地址绑定到绝对地址上，例如：74014
⚫ Each binding maps one address space to another
每个绑定都将一个地址空间映射到另一个地址空间

Binding of Instructions and Data to Memory
◼ Address binding of instructions and data to memory addresses can happen at three different stages
指令和数据与存储器的地址绑定 地址的绑定可以发生在三个不同的阶段
 Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes
编译时。如果内存位置是事先知道的。可以生成绝对代码；如果起始位置改变，必须重新编译 如果起始位置改变，必须重新编译代码
 Load time: Must generate relocatable code if memory location is not known at compile time
加载时间。必须生成可重定位的代码，如果 必须生成可重定位的代码，如果在编译时不知道内存位置
 Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers)
执行时间。如果进程在执行过程中可以从一个地方移动到另一个地方，则绑定时间将推迟到运行时间。进程在其执行过程中可以从一个 进程可以从一个内存段移动到另一个内存段。需要硬件支持 地址映射（例如，基数和极限寄存器）的硬件支持。

Dynamic Storage-Allocation Problem

◼ First-fit: Allocate the first hole that is big enough
◼ Best-fit: Allocate the smallest hole that is big enough;
must search entire list, unless ordered by size
 Produces the smallest leftover hole
◼ Worst-fit: Allocate the largest hole; must also search
entire list
 Produces the largest leftover hole
◼ First-fit and best-fit are better than worst-fit in terms of
speed and storage utilization

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Question:

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Practice:

1.No 2.Best Fit algorithm

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Paging：
Physical address space of a process can be noncontiguous; process
is allocated physical memory whenever the latter is available
◼ Divide physical memory into fixed-sized blocks called
frames (size is power of 2, between 512 bytes and 8,192
bytes)
◼ Divide logical memory into blocks of same size called pages
◼ Keep track of all free frames
◼ To run a program of size N pages, need to find N free frames and
load the program into them
◼ Set up a page table to translate logical to physical addresses
◼ Backing store likewise split into pages

Address Translation Scheme:
◼ Address generated by CPU is divided into 2 pieces:
 Page number页号 § – used as an index into a page table which
contains base address of each page in physical memory
 Page offset 页面偏移量(d) – combined with base address to define the
physical memory address that is sent to the memory unit

 For given logical address space 2m (m bits) and page size 2n

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1 KB=2^10=1024
1 MB=2^20
1 GB=2^30
1 TB=2^40

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◼ If the address of a given logical address space is A, the
page size is L, then page number P and page offset d
can be calculated as:
 P=INT⌊ A/L ⌋
 d=A MOD L
 For example, if the page size is 1KB, A=2170, then Address Translation Scheme
29
P=2, d=122

◼ Address translation(p, d)
 If p is in associative register, return corresponding frame number如果p是在关联寄存器中，则返回相应的帧号号码
 Otherwise get frame number from page table in memory 否则从内存中的页表获取帧号

Implementation of Page Table
◼ Page table is kept in main memory
页表被保存在主内存中
◼ Page-table base register (PTBR) points to the page table
页表基寄存器（PTBR）指向页表
◼ Page-table length register (PTLR) indicates size of the page table
页表长度寄存器（PTLR）表示页表的大小。
◼ In this scheme every data/instruction access requires two memory accesses: one for the page table and one for the data/instruction
在这个方案中，每个数据/指令访问都需要两次内存访问 ◼ 在这个方案中，每个数据/指令访问需要两个内存访问：一个是页表，一个是数据/指令。
◼ The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)
两个内存访问的问题可以通过使用一个特殊的快速查找硬件缓存来解决。这两个内存访问问题可以通过使用特殊的快速查找硬件缓冲器来解决，这种硬件缓冲器称为关联内存或 翻译查找缓冲器（TLB）。
◼ Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process to provide address-space protection for that process
有些TLB在每个TLB中存储地址空间标识符（ASIDs） 条目 - 唯一识别每个进程以提供地址空间的 为该进程提供地址空间保护

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Effective Access Time
◼ Associative Lookup = t time unit
◼ Hit ratio = 
 Hit ratio – percentage of times that a page number is found in the
associative registers; ratio related to number of associative registers
◼ Consider  = 80, 100ns for memory access
◼ Effective Access Time (EAT)
◼ Consider  = 80%, 100ns for memory access
 EAT = 0.80 x 100 + 0.20 x 200 = 120ns
◼ Consider more realistic hit ratio ->  = 99%, 100ns for memory access
EAT = 0.99 x 100 + 0.01 x 200 = 101ns

◼ Multi-level TLBs (data & instruction)
 L1
 L2

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Structure of the Page Table
◼ Memory structures for paging can get huge using
straightforward methods
◼ Hierarchical Paging
◼ Hashed Page Tables
◼ Inverted Page Tables

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(1).Page number and Page offset
(2).C
(3).P=0 d=500

3*1024+512=3584