TMP117
发送指令16'h91_00，‘b1000 0001是设备地址，’b0000_0000是寄存器地址
读时序：
//==================================================================================================================
// COMPANY : ABAX
// ENGINEER : jinjing
// CREATE DATE : 2021/04/20
// PROJECT NAME :
// TARGET DEVICES :
// TOOL VERSIONS : XILINX VIVADO 2018.3
// DESCRIPTION : TMP117温度传感器读逻辑，100KHZ
//==================================================================================================================
module IICR_TMP117(
//SYSTEM INPUT
input clk_100m , //操作时钟，100Mhz
input clk_rst_n , //时钟复位，低有效
//USER INPUT
input [15:0] tmp117_txd , //TMP117命令
input tmp117_txd_en , //TMP117命令有效，一个周期高电平
input tmp117_sda_in , //IIC数据输入
//USER OUTPUT
output tmp117_scl , //TMP117 IIC随路时钟
output tmp117_sda_out , //TMP117 IIC数据
output reg tmp117_sda_link , //TMP117 IIC链接状态
output reg [15:0] tmp117_rxd , //温度数据
output reg tmp117_rxd_valid //温度数据有效，一个周期高电平
);
//==================================================================================================
// parameter
//==================================================================================================
localparam IIC_CNT_MAX = 32'd49000;
localparam IIC_BIT_CNT_MAX = 32'd1000;
//==================================================================================================
// reg & wire
//==================================================================================================
reg [15:0] tmp117_txd_buf ;
reg [2 :0] iic_rstate ;
reg [31:0] iic_rstate_cnt ;
reg [31:0] iic_bit_cnt ;
reg [5 :0] iic_bit ;
reg iic_sda_out ;
reg iic_sda_rstart ;
//==================================================================================================
// main code
//==================================================================================================
// 缓存IIC控制指令
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
tmp117_txd_buf <= 16'd0;
else
tmp117_txd_buf <= tmp117_txd_en ? tmp117_txd : tmp117_txd_buf;
end
// IIC读state
always@(posedge clk_100m or negedge clk_rst_n)
begin
if (!clk_rst_n)
iic_rstate <= 3'd0;
else
case(iic_rstate)
3'd0 : iic_rstate <= tmp117_txd_en ? iic_rstate + 3'd1 : iic_rstate; //缓存状态
3'd1 : iic_rstate <= ( iic_rstate_cnt >= IIC_CNT_MAX ) ? iic_rstate + 3'd1 : iic_rstate; //读取IIC数据
3'd2 : iic_rstate <= iic_rstate + 3'd1;
3'd3 : iic_rstate <= iic_rstate + 3'd1;
3'd4 : iic_rstate <= iic_rstate + 3'd1;
3'd5 : iic_rstate <= iic_rstate + 3'd1;
default : iic_rstate <= 3'd0;
endcase
end
//IIC state cnt 状态计数器，控制状态转移
always@(posedge clk_100m or negedge clk_rst_n)
begin
if (!clk_rst_n)
iic_rstate_cnt <= 32'd0;
else
iic_rstate_cnt <= ( iic_rstate == 3'd1 ) ? iic_rstate_cnt + 32'd1 : 32'd0;
end
always@(posedge clk_100m or negedge clk_rst_n)
begin
if (!clk_rst_n)
iic_bit_cnt <= 32'd0;
else
iic_bit_cnt <= ( iic_rstate == 3'd1 ) && ( iic_bit_cnt <= IIC_BIT_CNT_MAX - 32'd1 ) ? iic_bit_cnt + 32'd1 : 32'd0;
end
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
iic_bit <= 6'd0;
else begin
if(iic_rstate == 3'd1)
iic_bit <= ( iic_bit_cnt == IIC_BIT_CNT_MAX - 32'd1 ) ? iic_bit + 6'd1 : iic_bit;
else
iic_bit <= 6'd0;
end
end
assign tmp117_scl = ( iic_bit >= 6'd1 ) && ( iic_bit <= 6'd47 ) &&
( iic_bit_cnt >= ( IIC_BIT_CNT_MAX >> 1 ) ) && ( iic_bit_cnt <= ( IIC_BIT_CNT_MAX - 32'd1 ) ) ? 0 : 1;
// tmp117_sda
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
iic_sda_out <= 1;
else begin
if(iic_rstate == 3'd1) begin
if( iic_bit_cnt == (( IIC_BIT_CNT_MAX >> 1 ) + ( IIC_BIT_CNT_MAX >> 2 )))
case( iic_bit )
6'd0 : iic_sda_out <= 1'b0; // iic start
6'd1 : iic_sda_out <= tmp117_txd_buf[15];
6'd2 : iic_sda_out <= tmp117_txd_buf[14];
6'd3 : iic_sda_out <= tmp117_txd_buf[13];
6'd4 : iic_sda_out <= tmp117_txd_buf[12];
6'd5 : iic_sda_out <= tmp117_txd_buf[11];
6'd6 : iic_sda_out <= tmp117_txd_buf[10];
6'd7 : iic_sda_out <= tmp117_txd_buf[9 ];
6'd8 : iic_sda_out <= 0;
6'd9 : iic_sda_out <= 1'b0; // z
6'd10 : iic_sda_out <= tmp117_txd_buf[7 ];
6'd11 : iic_sda_out <= tmp117_txd_buf[6 ];
6'd12 : iic_sda_out <= tmp117_txd_buf[5 ];
6'd13 : iic_sda_out <= tmp117_txd_buf[4 ];
6'd14 : iic_sda_out <= tmp117_txd_buf[3 ];
6'd15 : iic_sda_out <= tmp117_txd_buf[2 ];
6'd16 : iic_sda_out <= tmp117_txd_buf[1 ];
6'd17 : iic_sda_out <= tmp117_txd_buf[0 ];
6'd18 : iic_sda_out <= 0; // stop
6'd19 : iic_sda_out <= 0; // restart
6'd20 : iic_sda_out <= tmp117_txd_buf[15];
6'd21 : iic_sda_out <= tmp117_txd_buf[14];
6'd22 : iic_sda_out <= tmp117_txd_buf[13];
6'd23 : iic_sda_out <= tmp117_txd_buf[12];
6'd24 : iic_sda_out <= tmp117_txd_buf[11];
6'd25 : iic_sda_out <= tmp117_txd_buf[10];
6'd26 : iic_sda_out <= tmp117_txd_buf[9 ];
6'd27 : iic_sda_out <= tmp117_txd_buf[8 ];
6'd28 : iic_sda_out <= 0; // z
6'd29 : iic_sda_out <= 0; // iic data
6'd30 : iic_sda_out <= 0;
6'd31 : iic_sda_out <= 0;
6'd32 : iic_sda_out <= 0;
6'd33 : iic_sda_out <= 0;
6'd34 : iic_sda_out <= 0;
6'd35 : iic_sda_out <= 0;
6'd36 : iic_sda_out <= 0;
6'd37 : iic_sda_out <= 0; // z
6'd38 : iic_sda_out <= 0;
6'd39 : iic_sda_out <= 0;
6'd40 : iic_sda_out <= 0;
6'd41 : iic_sda_out <= 0;
6'd42 : iic_sda_out <= 0;
6'd43 : iic_sda_out <= 0;
6'd44 : iic_sda_out <= 0;
6'd45 : iic_sda_out <= 0;
6'd46 : iic_sda_out <= 1; // no ack
6'd47 : iic_sda_out <= 0; // iic stop
6'd48 : iic_sda_out <= 1; // iic stop
default : iic_sda_out <= 1;
endcase
else
iic_sda_out <= iic_sda_out;
end
else
iic_sda_out <= 1;
end
end
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
iic_sda_rstart <= 1'b0;
else begin
if(( iic_bit == 6'd19 ) && ( iic_bit_cnt == (( IIC_BIT_CNT_MAX >> 1 ) + (IIC_BIT_CNT_MAX >> 2 )+ 1 )))
iic_sda_rstart <= 1'b1;
else if( ( iic_bit == 6'd20 ) && ( iic_bit_cnt == (IIC_BIT_CNT_MAX >> 2 ) ) )
iic_sda_rstart <= 1'b0;
else
iic_sda_rstart <= iic_sda_rstart;
end
end
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
tmp117_sda_link <= 0;
else begin
if( iic_rstate == 3'd1 ) begin
if( iic_bit_cnt == (( IIC_BIT_CNT_MAX >> 1 ) + (IIC_BIT_CNT_MAX >> 2 )) )
case( iic_bit )
6'd0 : tmp117_sda_link <= 0;
6'd9 : tmp117_sda_link <= 1;
6'd10 : tmp117_sda_link <= 0;
6'd18 : tmp117_sda_link <= 1;
6'd19 : tmp117_sda_link <= 0;
6'd28 : tmp117_sda_link <= 1;
6'd29 : tmp117_sda_link <= 1;
6'd30 : tmp117_sda_link <= 1;
6'd31 : tmp117_sda_link <= 1;
6'd32 : tmp117_sda_link <= 1;
6'd33 : tmp117_sda_link <= 1;
6'd34 : tmp117_sda_link <= 1;
6'd35 : tmp117_sda_link <= 1;
6'd36 : tmp117_sda_link <= 1;
6'd37 : tmp117_sda_link <= 0;
6'd38 : tmp117_sda_link <= 1;
6'd39 : tmp117_sda_link <= 1;
6'd40 : tmp117_sda_link <= 1;
6'd41 : tmp117_sda_link <= 1;
6'd42 : tmp117_sda_link <= 1;
6'd43 : tmp117_sda_link <= 1;
6'd44 : tmp117_sda_link <= 1;
6'd45 : tmp117_sda_link <= 1;
6'd46 : tmp117_sda_link <= 0;
6'd47 : tmp117_sda_link <= 0;
default : tmp117_sda_link <= 0;
endcase
else
tmp117_sda_link <= tmp117_sda_link;
end
else
tmp117_sda_link <= 0;
end
end
assign tmp117_sda_out = iic_sda_out || iic_sda_rstart;
//FPGA从IIC SDA读出的数据
reg tmp117_sda_in_r;
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
tmp117_sda_in_r <= 1'b0;
else
tmp117_sda_in_r <= tmp117_sda_in;
end
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
tmp117_rxd <= 16'd0;
else begin
if( iic_rstate == 3'd1 ) begin
if( iic_bit_cnt == ( IIC_BIT_CNT_MAX >> 2 ) )
case( iic_bit )
6'd30 : tmp117_rxd[15] <= tmp117_sda_in_r;
6'd31 : tmp117_rxd[14] <= tmp117_sda_in_r;
6'd32 : tmp117_rxd[13] <= tmp117_sda_in_r;
6'd33 : tmp117_rxd[12] <= tmp117_sda_in_r;
6'd34 : tmp117_rxd[11] <= tmp117_sda_in_r;
6'd35 : tmp117_rxd[10] <= tmp117_sda_in_r;
6'd36 : tmp117_rxd[9 ] <= tmp117_sda_in_r;
6'd37 : tmp117_rxd[8 ] <= tmp117_sda_in_r;
6'd39 : tmp117_rxd[7 ] <= tmp117_sda_in_r;
6'd40 : tmp117_rxd[6 ] <= tmp117_sda_in_r;
6'd41 : tmp117_rxd[5 ] <= tmp117_sda_in_r;
6'd42 : tmp117_rxd[4 ] <= tmp117_sda_in_r;
6'd43 : tmp117_rxd[3 ] <= tmp117_sda_in_r;
6'd44 : tmp117_rxd[2 ] <= tmp117_sda_in_r;
6'd45 : tmp117_rxd[1 ] <= tmp117_sda_in_r;
6'd46 : tmp117_rxd[0 ] <= tmp117_sda_in_r;
default : tmp117_rxd <= tmp117_rxd;
endcase
else
tmp117_rxd <= tmp117_rxd;
end
else
tmp117_rxd <= tmp117_rxd;
end
end
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
tmp117_rxd_valid <= 1'b0;
else
tmp117_rxd_valid <= (iic_rstate == 3'd6) ? 1'b1 : 1'b0;
end
endmodule
ADS1100
配置寄存器
ST/BSY确定读写。
SC控制ADS1100是处于连续转换模式还是处于单次转换模式。当SC为1时，ADS1100处于单次转换模式；当SC为0时，ADS1100处于连续转换模式。默认设置为0。
DR控制采样速率。
PGA控制增益。
输出寄存器
R/W位1为写；
start by master SDA总线给主机，主机发数据，link=0；
ACK By ADS1100 SDA总线给从机 ，从机发数据，link=1，此时为高阻态；
// tmp117_sda
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
iic_sda_out <= 1;
else begin
if(iic_rstate == 3'd1) begin
if( iic_bit_cnt == (( IIC_BIT_CNT_MAX >> 1 ) + ( IIC_BIT_CNT_MAX >> 2 )))
case( iic_bit )
6'd0 : iic_sda_out <= 1'b0; // iic start
6'd1 : iic_sda_out <= tmp117_txd_buf[15];
6'd2 : iic_sda_out <= tmp117_txd_buf[14];
6'd3 : iic_sda_out <= tmp117_txd_buf[13];
6'd4 : iic_sda_out <= tmp117_txd_buf[12];
6'd5 : iic_sda_out <= tmp117_txd_buf[11];
6'd6 : iic_sda_out <= tmp117_txd_buf[10];
6'd7 : iic_sda_out <= tmp117_txd_buf[9 ];
6'd8 : iic_sda_out <= 1'b1; //ads1100 1是读 0是写 读写位
6'd9 : iic_sda_out <= 1'b0; // z 应答位 从机应答
6'd10 : iic_sda_out <= 'b0; // 接收高八位 link设置为z高阻态 iic data
6'd11 : iic_sda_out <= 'b0; // 接收高八位 link设置为z高阻态
6'd12 : iic_sda_out <= 'b0; // 接收高八位 link设置为z高阻态
6'd13 : iic_sda_out <= 'b0; // 接收高八位 link设置为z高阻态
6'd14 : iic_sda_out <= 'b0; // 接收高八位 link设置为z高阻态
6'd15 : iic_sda_out <= 'b0; // 接收高八位 link设置为z高阻态
6'd16 : iic_sda_out <= 'b0; // 接收高八位 link设置为z高阻态
6'd17 : iic_sda_out <= 'b0; // 接收高八位 link设置为z高阻态
6'd18 : iic_sda_out <= 0; // stop 应答位
6'd19 : iic_sda_out <= 'b0; // 接收di八位 link设置为z高阻态
6'd20 : iic_sda_out <= 'b0; // 接收di八位 link设置为z高阻态
6'd21 : iic_sda_out <= 'b0; // 接收di八位 link设置为z高阻态
6'd22 : iic_sda_out <= 'b0; // 接收di八位 link设置为z高阻态
6'd23 : iic_sda_out <= 'b0; // 接收di八位 link设置为z高阻态
6'd24 : iic_sda_out <= 'b0; // 接收di八位 link设置为z高阻态
6'd25 : iic_sda_out <= 'b0; // 接收di八位 link设置为z高阻态
6'd26 : iic_sda_out <= 'b0; // 接收di八位 link设置为z高阻态
6'd27 : iic_sda_out <= 0; //z
6'd28 : iic_sda_out <= 'b0; // 接收8bit配置信息
6'd29 : iic_sda_out <= 'b0; // 接收8bit配置信息
6'd30 : iic_sda_out <= 'b0; // 接收8bit配置信息
6'd31 : iic_sda_out <= 'b0; // 接收8bit配置信息
6'd32 : iic_sda_out <= 'b0; // 接收8bit配置信息
6'd33 : iic_sda_out <= 'b0; // 接收8bit配置信息
6'd34 : iic_sda_out <= 'b0; // 接收8bit配置信息
6'd35 : iic_sda_out <= 'b0; // 接收8bit配置信息
6'd36 : iic_sda_out <= 0; //z
6'd37 : iic_sda_out <= 1; // // iic stop
// 6'd38 : iic_sda_out <= 0;
// 6'd39 : iic_sda_out <= 0;
// 6'd40 : iic_sda_out <= 0;
// 6'd41 : iic_sda_out <= 0;
// 6'd42 : iic_sda_out <= 0;
// 6'd43 : iic_sda_out <= 0;
// 6'd44 : iic_sda_out <= 0;
// 6'd45 : iic_sda_out <= 0;
// 6'd46 : iic_sda_out <= 1; // no ack
// 6'd47 : iic_sda_out <= 0; // iic stop
// 6'd48 : iic_sda_out <= 1; // iic stop
default : iic_sda_out <= 1;
endcase
else
iic_sda_out <= iic_sda_out;
end
else
iic_sda_out <= 1;
end
end发数据的代码；
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
tmp117_sda_link <= 0;
else begin
if( iic_rstate == 3'd1 ) begin
if( iic_bit_cnt == (( IIC_BIT_CNT_MAX >> 1 ) + (IIC_BIT_CNT_MAX >> 2 )) )
case( iic_bit )
6'd0 : tmp117_sda_link <= 0; // 0 data
6'd9 : tmp117_sda_link <= 1; // 1 释放总线 为高阻态
6'd10 : tmp117_sda_link <= 1;
6'd11 : tmp117_sda_link <= 1;
6'd12 : tmp117_sda_link <= 1;
6'd13 : tmp117_sda_link <= 1;
6'd14 : tmp117_sda_link <= 1;
6'd15 : tmp117_sda_link <= 1;
6'd16 : tmp117_sda_link <= 1;
6'd17 : tmp117_sda_link <= 1;
6'd18 : tmp117_sda_link <= 0;
6'd19 : tmp117_sda_link <= 1;
6'd20 : tmp117_sda_link <= 1;
6'd21 : tmp117_sda_link <= 1;
6'd22 : tmp117_sda_link <= 1;
6'd23 : tmp117_sda_link <= 1;
6'd24 : tmp117_sda_link <= 1;
6'd25 : tmp117_sda_link <= 1;
6'd26 : tmp117_sda_link <= 1;
6'd27 : tmp117_sda_link <= 0;
6'd28 : tmp117_sda_link <= 1;
6'd29 : tmp117_sda_link <= 1;
6'd30 : tmp117_sda_link <= 1;
6'd31 : tmp117_sda_link <= 1;
6'd32 : tmp117_sda_link <= 1;
6'd33 : tmp117_sda_link <= 1;
6'd34 : tmp117_sda_link <= 1;
6'd35 : tmp117_sda_link <= 1;
6'd36 : tmp117_sda_link <= 0;
6'd37 : tmp117_sda_link <= 0;
// 6'd38 : tmp117_sda_link <= 1;
// 6'd39 : tmp117_sda_link <= 1;
// 6'd40 : tmp117_sda_link <= 1;
// 6'd41 : tmp117_sda_link <= 1;
// 6'd42 : tmp117_sda_link <= 1;
// 6'd43 : tmp117_sda_link <= 1;
// 6'd44 : tmp117_sda_link <= 1;
// 6'd45 : tmp117_sda_link <= 1;
// 6'd46 : tmp117_sda_link <= 0;
// 6'd47 : tmp117_sda_link <= 0;
default : tmp117_sda_link <= 0;
endcase
else
tmp117_sda_link <= tmp117_sda_link;
end
else
tmp117_sda_link <= 0;
end
end
assign tmp117_sda_out = iic_sda_out || iic_sda_rstart;控制连接；
MCP4107
iic写格式
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2024/05/13 17:02:11
// Design Name:
// Module Name: MCP4017
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module MCP4017(
//SYSTEM INPUT
input clk_100m , //操作时钟，100Mhz
input clk_rst_n , //时钟复位，低有效
//USER INPUT
input [15:0] tmp117_txd , //TMP117命令
input tmp117_txd_en , //TMP117命令有效，一个周期高电平
input tmp117_sda_in , //IIC数据输入
//USER OUTPUT
output tmp117_scl , //TMP117 IIC随路时钟
output tmp117_sda_out , //TMP117 IIC数据
output reg tmp117_sda_link , //TMP117 IIC链接状态
output reg [15:0] tmp117_rxd , //温度数据
output reg tmp117_rxd_valid //温度数据有效，一个周期高电平
);
//==================================================================================================
// parameter
//==================================================================================================
localparam IIC_CNT_MAX = 32'd49000;
localparam IIC_BIT_CNT_MAX = 32'd1000;
//==================================================================================================
// reg & wire
//==================================================================================================
reg [15:0] tmp117_txd_buf ;
reg [2 :0] iic_rstate ;
reg [31:0] iic_rstate_cnt ;
reg [31:0] iic_bit_cnt ;
reg [5 :0] iic_bit ;
reg iic_sda_out ;
reg iic_sda_rstart ;
//==================================================================================================
// main code
//==================================================================================================
// 缓存IIC控制指令
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
tmp117_txd_buf <= 16'd0;
else
tmp117_txd_buf <= tmp117_txd_en ? tmp117_txd : tmp117_txd_buf;
end
// IIC读state
always@(posedge clk_100m or negedge clk_rst_n)
begin
if (!clk_rst_n)
iic_rstate <= 3'd0;
else
case(iic_rstate)
3'd0 : iic_rstate <= tmp117_txd_en ? iic_rstate + 3'd1 : iic_rstate; //缓存状态
3'd1 : iic_rstate <= ( iic_rstate_cnt >= IIC_CNT_MAX ) ? iic_rstate + 3'd1 : iic_rstate; //读取IIC数据
3'd2 : iic_rstate <= iic_rstate + 3'd1;
3'd3 : iic_rstate <= iic_rstate + 3'd1;
3'd4 : iic_rstate <= iic_rstate + 3'd1;
3'd5 : iic_rstate <= iic_rstate + 3'd1;
default : iic_rstate <= 3'd0;
endcase
end
//IIC state cnt 状态计数器，控制状态转移
always@(posedge clk_100m or negedge clk_rst_n)
begin
if (!clk_rst_n)
iic_rstate_cnt <= 32'd0;
else
iic_rstate_cnt <= ( iic_rstate == 3'd1 ) ? iic_rstate_cnt + 32'd1 : 32'd0;
end
always@(posedge clk_100m or negedge clk_rst_n)
begin
if (!clk_rst_n)
iic_bit_cnt <= 32'd0;
else
iic_bit_cnt <= ( iic_rstate == 3'd1 ) && ( iic_bit_cnt <= IIC_BIT_CNT_MAX - 32'd1 ) ? iic_bit_cnt + 32'd1 : 32'd0;
end
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
iic_bit <= 6'd0;
else begin
if(iic_rstate == 3'd1)
iic_bit <= ( iic_bit_cnt == IIC_BIT_CNT_MAX - 32'd1 ) ? iic_bit + 6'd1 : iic_bit;
else
iic_bit <= 6'd0;
end
end
assign tmp117_scl = ( iic_bit >= 6'd1 ) && ( iic_bit <= 6'd19 ) &&
( iic_bit_cnt >= ( IIC_BIT_CNT_MAX >> 1 ) ) && ( iic_bit_cnt <= ( IIC_BIT_CNT_MAX - 32'd1 ) ) ? 0 : 1;
// tmp117_sda
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
iic_sda_out <= 1;
else begin
if(iic_rstate == 3'd1) begin
if( iic_bit_cnt == (( IIC_BIT_CNT_MAX >> 1 ) + ( IIC_BIT_CNT_MAX >> 2 )))
case( iic_bit )
6'd0 : iic_sda_out <= 1'b0; // iic start
6'd1 : iic_sda_out <= tmp117_txd_buf[15];
6'd2 : iic_sda_out <= tmp117_txd_buf[14];
6'd3 : iic_sda_out <= tmp117_txd_buf[13];
6'd4 : iic_sda_out <= tmp117_txd_buf[12];
6'd5 : iic_sda_out <= tmp117_txd_buf[11];
6'd6 : iic_sda_out <= tmp117_txd_buf[10];
6'd7 : iic_sda_out <= tmp117_txd_buf[9 ];
6'd8 : iic_sda_out <= 0; //* 写操作
6'd9 : iic_sda_out <= 1'b0; // z 从机应答 link = 1
6'd10 : iic_sda_out <= tmp117_txd_buf[7 ]; // * 高8位 无所谓
6'd11 : iic_sda_out <= tmp117_txd_buf[6 ]; //* 7位有效 0- 127
6'd12 : iic_sda_out <= tmp117_txd_buf[5 ]; //* 7位有效 0- 127
6'd13 : iic_sda_out <= tmp117_txd_buf[4 ]; //* 7位有效 0- 127
6'd14 : iic_sda_out <= tmp117_txd_buf[3 ]; //* 7位有效 0- 127
6'd15 : iic_sda_out <= tmp117_txd_buf[2 ]; //* 7位有效 0- 127
6'd16 : iic_sda_out <= tmp117_txd_buf[1 ]; //* 7位有效 0- 127
6'd17 : iic_sda_out <= tmp117_txd_buf[0 ]; //* 7位有效 0- 127
6'd18 : iic_sda_out <= 0; // z 从机应答 link = 1
6'd19 : iic_sda_out <= 0; // stop
6'd20 : iic_sda_out <= 1; // stop
// 6'd21 : iic_sda_out <= tmp117_txd_buf[14];
// 6'd22 : iic_sda_out <= tmp117_txd_buf[13];
// 6'd23 : iic_sda_out <= tmp117_txd_buf[12];
// 6'd24 : iic_sda_out <= tmp117_txd_buf[11];
// 6'd25 : iic_sda_out <= tmp117_txd_buf[10];
// 6'd26 : iic_sda_out <= tmp117_txd_buf[9 ];
// 6'd27 : iic_sda_out <= tmp117_txd_buf[8 ];
// 6'd28 : iic_sda_out <= 0; // z
// 6'd29 : iic_sda_out <= 0; // iic data
// 6'd30 : iic_sda_out <= 0;
// 6'd31 : iic_sda_out <= 0;
// 6'd32 : iic_sda_out <= 0;
// 6'd33 : iic_sda_out <= 0;
// 6'd34 : iic_sda_out <= 0;
// 6'd35 : iic_sda_out <= 0;
// 6'd36 : iic_sda_out <= 0;
// 6'd37 : iic_sda_out <= 0; // z
// 6'd38 : iic_sda_out <= 0;
// 6'd39 : iic_sda_out <= 0;
// 6'd40 : iic_sda_out <= 0;
// 6'd41 : iic_sda_out <= 0;
// 6'd42 : iic_sda_out <= 0;
// 6'd43 : iic_sda_out <= 0;
// 6'd44 : iic_sda_out <= 0;
// 6'd45 : iic_sda_out <= 0;
// 6'd46 : iic_sda_out <= 1; // no ack
// 6'd47 : iic_sda_out <= 0; // iic stop
// 6'd48 : iic_sda_out <= 1; // iic stop
default : iic_sda_out <= 1;
endcase
else
iic_sda_out <= iic_sda_out;
end
else
iic_sda_out <= 1;
end
end
//* always@(posedge clk_100m or negedge clk_rst_n)
//* begin
//* if(!clk_rst_n)
//* iic_sda_rstart <= 1'b0;
//* else begin
//* if(( iic_bit == 6'd19 ) && ( iic_bit_cnt == (( IIC_BIT_CNT_MAX >> 1 ) + (IIC_BIT_CNT_MAX >> 2 )+ 1 )))
//* iic_sda_rstart <= 1'b1;
//* else if( ( iic_bit == 6'd20 ) && ( iic_bit_cnt == (IIC_BIT_CNT_MAX >> 2 ) ) )
//* iic_sda_rstart <= 1'b0;
//* else
//* iic_sda_rstart <= iic_sda_rstart;
//* end
//* end
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
tmp117_sda_link <= 0;
else begin
if( iic_rstate == 3'd1 ) begin
if( iic_bit_cnt == (( IIC_BIT_CNT_MAX >> 1 ) + (IIC_BIT_CNT_MAX >> 2 )) )
case( iic_bit )
6'd0 : tmp117_sda_link <= 0;
6'd9 : tmp117_sda_link <= 1;
6'd10 : tmp117_sda_link <= 0;
6'd18 : tmp117_sda_link <= 1;
6'd19 : tmp117_sda_link <= 0;
//* 6'd28 : tmp117_sda_link <= 1;
//* 6'd29 : tmp117_sda_link <= 1;
//* 6'd30 : tmp117_sda_link <= 1;
//* 6'd31 : tmp117_sda_link <= 1;
//* 6'd32 : tmp117_sda_link <= 1;
//* 6'd33 : tmp117_sda_link <= 1;
//* 6'd34 : tmp117_sda_link <= 1;
//* 6'd35 : tmp117_sda_link <= 1;
//* 6'd36 : tmp117_sda_link <= 1;
//* 6'd37 : tmp117_sda_link <= 0;
//* 6'd38 : tmp117_sda_link <= 1;
//* 6'd39 : tmp117_sda_link <= 1;
//* 6'd40 : tmp117_sda_link <= 1;
//* 6'd41 : tmp117_sda_link <= 1;
//* 6'd42 : tmp117_sda_link <= 1;
//* 6'd43 : tmp117_sda_link <= 1;
//* 6'd44 : tmp117_sda_link <= 1;
//* 6'd45 : tmp117_sda_link <= 1;
//* 6'd46 : tmp117_sda_link <= 0;
//* 6'd47 : tmp117_sda_link <= 0;
default : tmp117_sda_link <= 0;
endcase
else
tmp117_sda_link <= tmp117_sda_link;
end
else
tmp117_sda_link <= 0;
end
end
assign tmp117_sda_out = iic_sda_out ;//|| iic_sda_rstart;
//FPGA从IIC SDA读出的数据
reg tmp117_sda_in_r;
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
tmp117_sda_in_r <= 1'b0;
else
tmp117_sda_in_r <= tmp117_sda_in;
end
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
tmp117_rxd <= 16'd0;
else begin
if( iic_rstate == 3'd1 ) begin
if( iic_bit_cnt == ( IIC_BIT_CNT_MAX >> 2 ) )
case( iic_bit )
6'd30 : tmp117_rxd[15] <= tmp117_sda_in_r;
6'd31 : tmp117_rxd[14] <= tmp117_sda_in_r;
6'd32 : tmp117_rxd[13] <= tmp117_sda_in_r;
6'd33 : tmp117_rxd[12] <= tmp117_sda_in_r;
6'd34 : tmp117_rxd[11] <= tmp117_sda_in_r;
6'd35 : tmp117_rxd[10] <= tmp117_sda_in_r;
6'd36 : tmp117_rxd[9 ] <= tmp117_sda_in_r;
6'd37 : tmp117_rxd[8 ] <= tmp117_sda_in_r;
6'd39 : tmp117_rxd[7 ] <= tmp117_sda_in_r;
6'd40 : tmp117_rxd[6 ] <= tmp117_sda_in_r;
6'd41 : tmp117_rxd[5 ] <= tmp117_sda_in_r;
6'd42 : tmp117_rxd[4 ] <= tmp117_sda_in_r;
6'd43 : tmp117_rxd[3 ] <= tmp117_sda_in_r;
6'd44 : tmp117_rxd[2 ] <= tmp117_sda_in_r;
6'd45 : tmp117_rxd[1 ] <= tmp117_sda_in_r;
6'd46 : tmp117_rxd[0 ] <= tmp117_sda_in_r;
default : tmp117_rxd <= tmp117_rxd;
endcase
else
tmp117_rxd <= tmp117_rxd;
end
else
tmp117_rxd <= tmp117_rxd;
end
end
always@(posedge clk_100m or negedge clk_rst_n)
begin
if(!clk_rst_n)
tmp117_rxd_valid <= 1'b0;
else
tmp117_rxd_valid <= (iic_rstate == 3'd6) ? 1'b1 : 1'b0;
end
endmodule
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