HDLBits_Serial Reciver and Datapath

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output [7:0] out_byte,
    output done
); //
    parameter [1:0] s0 = 2'b00,//idle
    				s1 = 2'b01,//data_in
    				s2 = 2'b11,//error
    				s3 = 2'b10;//done
    reg [1:0] state,next_state;
    reg done_reg;
    reg [7:0] out_byte_reg_temp,out_byte_reg;
    integer  count;
    // Use FSM from Fsm_serial
    always @(*) begin
        case (state) 
            s0: begin
                out_byte_reg_temp<=8'b00000000;
                if(!in)
                    next_state = s1;
                else
                    next_state = s0;
            end
            
            s1:begin
                if(count<8) begin
                    next_state = s1;
                    out_byte_reg_temp[count]<=in ;
                end
                else if((count==8) & in)
                    next_state = s3;
                else
                    next_state = s2;
            end
            
            s2:begin
                out_byte_reg_temp<=8'b00000000;
                if(in)
                    next_state = s0;
                else
                    next_state = s2;
            end
            
            s3:begin
                out_byte_reg_temp<=8'b00000000;
                if(in) 
                    next_state = s0;
                else
                    next_state = s1;
            end
        endcase
    end
    
    always @(posedge clk) begin
        if(reset) begin
           	state<=s0;
            count<=0;

        end
        else begin
            case(state)
                s1:begin count<=count+1;out_byte_reg[count]<=out_byte_reg_temp[count];end
                default:begin count<=0;out_byte_reg<=8'b00000000;end
            endcase
        	state<=next_state;
        end

    end
    // New: Datapath to latch input bits.
	assign out_byte = out_byte_reg;
    assign done = (state==s3);
endmodule

//逻辑功能没问题

//但out_byte_reg_temp中会生成latch。但always@(*)内每个case明明都赋值了，加上default再赋值也还是会生成latch。求大神解答