HDLBits_Exams/2013 q2bfsm

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input x,
    input y,
    output  f,
    output  g
); 
    parameter [3:0] A=0,B=1,C=2,D=3,E=4,F=5,G=6,H=7;
    reg [3:0] state,next_state;
    reg count;
    
    always @(*) begin
        case(state)
           	A:next_state = resetn?B:A;
            B:next_state = C;
            C:next_state = x?D:C;
            D:next_state = x?D:E;
            E:next_state = x?F:C;
            F:begin
                if((!count)&y) next_state = G;
                else if((count)&y) next_state = G;
                else if(count & (!y)) next_state = H;
                else next_state = F;
            end
            G:next_state = G;
            H:next_state = H;
        endcase
    end
    
    always @(posedge clk) begin
        
        if( !resetn) begin
            count<=1'b0;
            state<=A;
        end
        
        else begin
           state<=next_state; 
            case(state)
                F:count <= count+1'b1;
                default:count<=1'b0;
            endcase
        end
        
    end
    
    always @(*) begin
        f = (state==B);
        g = (state==F) | (state==G);
    end
endmodule

A:reset状态

B:reset取消后第一次指示灯状态

C：指示灯结束，等待接收101信号前的空状态。接收1后跳转到D

DEF：101接收

F：空置等待y验证

G：有y到来，锁定g=1

H：无y到来，锁定g=0；

//更新

在F等待y检验过程中(always @(*) case:F )。这里查找了所有可能，对于多周期内y检验并不是实用，此处可以更新为：(num为需要在多少个周期内监测y=1)

            F:begin
                if((count==num-1)) begin
                    if(y) next_state = G;
                	else next_state = H;
                end
                else begin
                    if(y) next_state = G;
                	else  next_state = F;
                end
            end

但是这样也有问题，当count因为软错误跳转到比num-1大时，会陷入else。所以为了避免此情况，使用if（count <(num-1)）是最好的。但是综合后“<”会不会带来更大的面积损耗，有待商榷。

请大佬指导！