module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q);
reg [3:0] ones,tens,hundreds,thousands;
wire carry0,carry1,carry2,carry3;
wire [2:0]flag;
bcd bcdones(.clk(clk),.reset(reset),.cin(1'b1),.bcdcode(ones));
assign ena[1] = ones[0] & ones[3];
bcd bcdtens(.clk(clk),.reset(reset),.cin(ena[1]),.bcdcode(tens));
assign ena[2] = tens[3] & tens[0] & ones[0] & ones[3];
bcd bcdhundreds(.clk(clk),.reset(reset),.cin(ena[2]),.bcdcode(hundreds));
assign ena[3] = hundreds[0] & hundreds[3] & tens[3] & tens[0] & ones[0] & ones[3];
bcd bcdthousands(.clk(clk),.reset(reset),.cin(ena[3]),.bcdcode(thousands));assign q = {thousands,hundreds,tens,ones};
endmodulemodule bcd(
input clk,reset,cin,
output [3:0] bcdcode
);
always @(posedge clk) begin
if(reset) begin
bcdcode<=0;
end
else begin
if((bcdcode[3] & bcdcode[0])==1 & cin) begin
bcdcode <=0;
end
else if(bcdcode[3]) begin
bcdcode <=bcdcode +cin;
end
else begin
bcdcode <=bcdcode +cin;
end
end
end
endmodule
Countbcd—HDLBits
于 2024-03-27 15:18:28 首次发布