期末实验作业

一：代码：
module adder4(carryin,x3,x2,x1,x0,y3,y2,y1,y0,s3,s2,s1,s0,carryout);
input carryin,x3,x2,x1,x0,y3,y2,y1,y0;
output s3,s2,s1,s0,carryout;

fulladd stage0 (carryin,x0,y0,s0,c1);
fulladd stage1 (c1,x1,y1,s1,c2);
fulladd stage2 (c2,x2,y2,s2,c3);
fulladd stage3 (c3,x3,y3,s3,carryout);

endmodule

module fulladd(Cin,x,y,s,Cout);
input Cin,x,y;
output s,Cout;

assign s=x^yCin;
assign Cout=(x&y)|(x&Cin)|(y&Cin);

endmodule

二：Quartus II测试
1.创建Verilog HDL file
2.填写上述代码
3.进行编译
三：实验结果

五：
过程链接：https://www.bilibili.com/video/BV1m64y1t7VV/

一：代码·module Add_full_unit_delay(output c_out,sum,input a,b,c_in);
wire w1,w2,w3;
ADD_half_unit_delay M1(w2,w1,a,b);
ADD_half_unit_delay M2(w3,sum,w1,c_in);
or #1 M3(c_out,w2,w3);
endmodule
module ADD_half_unit_delay (output c_out,sum,input a,b);
xor #1 M1(sum,a,b);
and #1 M2(c_out,a,b);
endmodule

二:
1.在QuartusII中创建代码文件
2.输入上述代码
3.结果如图：
三.波形图
1.创建
2.单机空白处
3.添加随机输入信号
4.结果截图

一.代码
module digital(TimerH,TimerL,over,Reset,Stop,clk);
output [6:0]TimerH;
output [6:0]TimerL;
output over;
input Reset;
input Stop;
input clk;
wire [1:0]H;
wire [3:0]L;
wire clk_1;
fenpin UO (.clk(clk),.clk_old(clk_1));
basketballtimer U1(over, H[1:0],L[3:0], Reset, Stop,clk_1);
CD4511 U2 (TimerH[6:0], {2’b00,H[1:0]});
CD4511 U3 (TimerL[6:0], L[3:0]);
endmodule

module fenpin (clk_old, clk);
output clk_old;
input clk;
reg[24:0] count;
reg clk_old;
always @(posedge clk)
begin
if(count==25’b1_1001_0000_0000_0000_0000_0000)
begin
clk_old<=~clk_old;
count<=0;
end
else
count<=count+1;
end

endmodule

module basketballtimer (Over,TimerH, TimerL,Reset,Stop,clk_1);
output Over;
output [1:0]TimerH;
output [3:0]TimerL;
input Reset;
input Stop;
input clk_1;

reg [4:0] Q;

assign Over =(Q== 5 'd0);
assign TimerH=Q/10;
assign TimerL=Q%10;

always @(posedge clk_1 or negedge Reset or negedge Stop)
begin
if(~Reset)
Q <= 5’d23;
else
begin
if(~Stop)
Q <= Q;
else
begin
if(Q>5’d0)
Q <= Q - 1’b1;
else
Q <=Q;
end
end
end
endmodule

module CD4511 (Y,A);
output reg [6:0]Y;
input [3:0]A;
always @(*)
begin
case(A)
4’d0: Y<=7’b1000_000;
4 'd1: Y<=7’b1111_001;
4 'd2: Y<=7’b0100_100;
4’d3: Y<=7’b0110_000;
4 'd4:Y<=7’b0011_001;
4 'd5: Y<=7’b0010_010;
4 'd6: Y<=7’b0000_010;
4 'd7: Y<=7’b1111_000;
4 'd8: Y<=7 'b0000_000;
4’d9: Y<=7’b0010_000;
default: Y<=7’b1000_000;
endcase
end
endmodule

module tbdigital;
wire [6:0]TimerH;
wire [6:0]TimerL;
wire over;
reg Reset;
reg Stop;
reg clk;
initial
begin
clk=0;
Reset=1;
Stop=1;
#10 Reset=0;
#20 Reset=1;
#200 Stop=0;
#50 Stop=1;
@ (posedge over);
#10 $stop;
end

always #5 clk=~clk;
digital idigital (TimerH, TimerL, over,Reset, Stop, clk);
endmodule

二：实验结果截
图