1.实验名称:门级建模
2.实验工具:
电脑和Quartur ii软件和modlsim软件。
3.实验过程:
第一步:打开modlsim。
第二步:新建 Project。
第三步:代码输入。
第四步:保存。
第五步:编译。
第六步:生成测试文件。
第七步:进行仿真。
第八步:进行调试。
实验代码及其结果:
module pp(shift, seg7, seg8, clk50Mhz, rst, af, aj, bf, bj);
output[4:0] shift;
output[6:0] seg7;
output[6:0] seg8;
input clk50Mhz;
input af;
input aj;
input bf;
input bj;
input rst;
reg[4:0] shift;
reg[6:0] seg7;
reg[6:0] seg8;
reg clk2hz;
reg[3:0] a_score, b_score;
reg[23:0] cnt;
reg a, b;
reg[4:0] shift_1;
always@(posedge clk50Mhz)
begin
if(cnt==24'd12500000)
begin
clk2hz=~clk2hz;
cnt<=0;
end
else
cnt<=cnt+1;
end
always@(posedge clk2hz)
begin
if(rst)
begin
a_score<=0;
b_score<=0;
a<=0;
b<=0;
shift_1<=0;
end
else
begin
if(!a&&!b&&af)
begin
a<=1;
shift_1<='b10000;
end
else if(!a&&!b&&bf)
begin
b<=1;
shift_1<='b00001;
end
else if(a&&!b)
begin
if(shift_1>'b00100)
begin
if(bj)
begin
a_score<=a_score+1;
a<=0;
b<=0;
shift_1<='b00000;
end
else
begin
shift_1[4:0]<=shift_1[4:0]>>1;
end
end
else if(shift_1=='b0)
begin
a_score<=a_score+1;
a<=0;
b<=0;
end
else
begin
if(bj)
begin
a<=0;
b<=1;
end
else
begin
shift_1[4:0]<=shift_1[4:0]>>1;
end
end
end
else if(b&&!a)
begin
if(shift_1<'b00100&&shift_1!='b0)
begin
if(aj)
begin
b_score<=b_score+1;
a<=0;
b<=0;
shift_1<='b00000;
end
else
begin
shift_1[4:0]<=shift_1[4:0]<< 1;
end
end
else if(shift_1=='b0)
begin
b_score<=b_score+1;
a<=0;
b<=0;
end
else
begin
if(aj)
begin
a<=1;
b<=0;
end
else
begin
shift_1[4:0]<=shift_1[4:0]<<1;
end
end
end
end
shift<=shift_1;
if(a_score=='b1011&&!rst)
begin
a_score<=a_score;
b_score<=b_score;
end
if(b_score=='b1011&&!rst)
begin
a_score<=a_score;
b_score<=b_score;
end
end
always@(posedge clk2hz)
begin
case(a_score[3:0])
'b0000: seg7[6:0]=7'b0000001;
'b0001: seg7[6:0]=7'b1001111;
'b0010: seg7[6:0]=7'b0010010;
'b0011: seg7[6:0]=7'b0000110;
'b0100: seg7[6:0]=7'b1001100;
'b0101: seg7[6:0]=7'b0100100;
'b0110: seg7[6:0]=7'b0100000;
'b0111: seg7[6:0]=7'b0001111;
'b1000: seg7[6:0]=7'b0000000;
'b1001: seg7[6:0]=7'b0000100;
default: seg7[6:0]='bx;
endcase
case(b_score[3:0])
'b0000: seg8[6:0]=7'b0000001;
'b0001: seg8[6:0]=7'b1001111;
'b0010: seg8[6:0]=7'b0010010;
'b0011: seg8[6:0]=7'b0000110;
'b0100: seg8[6:0]=7'b1001100;
'b0101: seg8[6:0]=7'b0100100;
'b0110: seg8[6:0]=7'b0100000;
'b0111: seg8[6:0]=7'b0001111;
'b1000: seg8[6:0]=7'b0000000;
'b1001: seg8[6:0]=7'b0000100;
default: seg8[6:0]='bx;
endcase
end
endmodule
module tbpp;
reg clk;
reg af;
reg aj;
reg bf;
reg bj;
reg reset;
wire[4:0] shift;
wire[6:0] seg7;
wire[6:0] seg8;
initial
begin
clk=0;
reset=0;
#10 reset=1;
#20 reset=0;
end
always #5 clk=~clk;
initial
begin
af=0;bf=0;
#40 bf=1;
#10 bf=0;
repeat (4) @(posedge clk);
#5 aj=1;
#10 aj=0;
repeat (3) @(posedge clk);
bj=1;
#10 bj=0;
#30;
@(posedge clk);
#5 bf=1;
#10 bf=0;
#100 $stop;
end
pp pp(shift,seg7,seg8,clk,reset,af,aj,bf,bj);
endmodule