往期博文
低密度奇偶校验码LDPC(一)——概述_什么是gallager构造-CSDN博客
低密度奇偶校验码LDPC(二)——LDPC编码方法-CSDN博客
低密度奇偶校验码LDPC(三)——QC-LDPC码概述-CSDN博客
低密度奇偶校验码LDPC(四)——双对角线结构的QC-LDPC编码-CSDN博客
低密度奇偶校验码LDPC(五)——译码算法概述-CSDN博客
低密度奇偶校验码LDPC(六)——SPA和积译码算法-CSDN博客
QC-LDPC的FPGA实现
基于QC-LDPC编码的循环移位网络的FPGA实现_5g ldpc编码 桶形移位寄存器-CSDN博客
循环移位
一、桶式移位寄存器(barrel shifter)
八位桶式移位寄存器的VHDL实现如下,由于每一层结构相似,于是采用生成语句for_generate实现,使用该代码实现的RTL级分析和理论的结构一致,仿真结果也符合预期。
entity barrel_shift is
GENERIC(DATA_WIDTH: INTEGER:=8;
CTRL_WIDTH: INTEGER:=3);
Port (DATA_IN: IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
CTRL: IN STD_LOGIC_VECTOR(CTRL_WIDTH-1 DOWNTO 0);
DATA_OUT: OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0)
);
end barrel_shift;
architecture Behavioral of barrel_shift is
SIGNAL LAYER_1_TEMP: STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
SIGNAL LAYER_2_TEMP: STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
SIGNAL LAYER_3_TEMP: STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
begin
LAYER_1:FOR I IN 0 TO 7 GENERATE
G1:IF I<=3 GENERATE
LAYER_1_TEMP(I)<=DATA_IN(I)WHEN CTRL(2)='0'ELSE DATA_IN(I+4);
END GENERATE G1;
G2:IF I>3 GENERATE
LAYER_1_TEMP(I)<=DATA_IN(I)WHEN CTRL(2)='0'ELSE DATA_IN(I-4);
END GENERATE G2;
END GENERATE LAYER_1;
LAYER_2:FOR I IN 0 TO 7 GENERATE
G3:IF I<=5 GENERATE
LAYER_2_TEMP(I)<=LAYER_1_TEMP(I)WHEN CTRL(1)='0'ELSE LAYER_1_TEMP(I+2);
END GENERATE G3;
G4:IF I>5 GENERATE
LAYER_2_TEMP(I)<=LAYER_1_TEMP(I)WHEN CTRL(1)='0'ELSE LAYER_1_TEMP(I-6);
END GENERATE G4;
END GENERATE LAYER_2;
LAYER_3:FOR I IN 0 TO 7 GENERATE
G5:IF I<=6 GENERATE
LAYER_3_TEMP(I)<=LAYER_2_TEMP(I)WHEN CTRL(0)='0'ELSE LAYER_2_TEMP(I+1);
END GENERATE G5;
G6:IF I>6 GENERATE
LAYER_3_TEMP(I)<=LAYER_2_TEMP(I)WHEN CTRL(0)='0'ELSE LAYER_2_TEMP(I-7);
END GENERATE G6;
END GENERATE LAYER_3;
DATA_OUT<=LAYER_3_TEMP;
end Behavioral;
二、QSN网络
2.1LSN网络
该网络的VHDL代码和RTL分析如下
entity LSN_9x8_network is
GENERIC(DATA_WIDTH: INTEGER:=9;
CTRL_WIDTH: INTEGER:=4);
Port (DATA_IN: IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0);
LSN_CTRL: IN STD_LOGIC_VECTOR(CTRL_WIDTH-1 DOWNTO 0);
DATA_OUT: OUT STD_LOGIC_VECTOR(DATA_WIDTH-2 DOWNTO 0)
);
end LSN_9x8_network;
architecture Behavioral of LSN_9x8_network is
SIGNAL LAYER_1_TEMP: STD_LOGIC_VECTOR(DATA_WIDTH-9 DOWNTO 0);
SIGNAL LAYER_2_TEMP: STD_LOGIC_VECTOR(DATA_WIDTH-5 DOWNTO 0);
SIGNAL LAYER_3_TEMP: STD_LOGIC_VECTOR(DATA_WIDTH-3 DOWNTO 0);
SIGNAL LAYER_4_TEMP: STD_LOGIC_VECTOR(DATA_WIDTH-2 DOWNTO 0);
begin
LAYER_1:FOR I IN 0 TO 0 GENERATE
G1:IF I=0 GENERATE
LAYER_1_TEMP(I)<=DATA_IN(I)WHEN LSN_CTRL(3)='0'ELSE DATA_IN(I+8);
END GENERATE G1;
END GENERATE LAYER_1;
LAYER_2:FOR I IN 0 TO 4 GENERATE--5
G2:IF I=0 GENERATE
LAYER_2_TEMP(I)<=LAYER_1_TEMP(I)WHEN LSN_CTRL(2)='0'ELSE DATA_IN(I+4);
END GENERATE G2;
G3:IF I>0 GENERATE
LAYER_2_TEMP(I)<=DATA_IN(I) WHEN LSN_CTRL(2)='0'ELSE DATA_IN(I+4);
END GENERATE G3;
END GENERATE LAYER_2;
LAYER_3:FOR I IN 0 TO 6 GENERATE--7
G4:IF I<=2 GENERATE
LAYER_3_TEMP(I)<=LAYER_2_TEMP(I)WHEN LSN_CTRL(1)='0'ELSE LAYER_2_TEMP(I+2);
END GENERATE G4;
G5:IF I>2 AND I<=4 GENERATE
LAYER_3_TEMP(I)<=LAYER_2_TEMP(I)WHEN LSN_CTRL(1)='0'ELSE DATA_IN(I+2);
END GENERATE G5;
G6:IF I>4 GENERATE
LAYER_3_TEMP(I)<=DATA_IN(I) WHEN LSN_CTRL(0)='0'ELSE DATA_IN(I+2);
END GENERATE G6;
END GENERATE LAYER_3;
LAYER_4:FOR I IN 0 TO 7 GENERATE---8
G7:IF I<=5 GENERATE
LAYER_4_TEMP(I)<=LAYER_3_TEMP(I)WHEN LSN_CTRL(0)='0'ELSE LAYER_3_TEMP(I+1);
END GENERATE G7;
G8:IF I=6 GENERATE
LAYER_4_TEMP(I)<=LAYER_3_TEMP(I)WHEN LSN_CTRL(0)='0'ELSE DATA_IN(I+1);
END GENERATE G8;
G9:IF I>6 GENERATE
LAYER_4_TEMP(I)<=DATA_IN(I) WHEN LSN_CTRL(0)='0'ELSE DATA_IN(I+1);
END GENERATE G9;
END GENERATE LAYER_4;
DATA_OUT<=LAYER_4_TEMP(DATA_WIDTH-2 DOWNTO 0);
end Behavioral;