一、不用结构体封装版
1、C语言运行环境构建（编写文件start.s）
1.1 设置处理器模式
设置6ULL处于SVC模式 下。设置CPSR寄存器的bit4-0，也就是M[4:0]为10011=0X13。读写状态寄存器需要用到MRS和MSR指令。MRS将CPSR寄存器数据读出到通用寄存器里面，MSR指令将通用寄存器的值写入到CPSR寄存器里面去。
1.2 设置sp指针
Sp可以指向内部RAM，也可以指向DDR，我们将其指向DDR。Sp设置到哪里？512MB的范围0x80000000~0x9FFFFFFF。栈大小，0x200000=2MB。处理器栈增长方式，对于A7而言是向下增长的。设置sp指向0x80200000。
1.3 跳转到C语言
使用b指令，跳转到C语言函数，比如main函数。
.global _start
_start:
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0x13
msr cpsr,r0
ldr sp,=0x80200000
b main
2、软件编写
#ifndef __MAIN_H
#define __MAIN_H
/*
* CCM 相关寄存器地址
*/
#define CCM_CCGR0 *((volatile unsigned int *)0X020C4068)
#define CCM_CCGR1 *((volatile unsigned int *)0X020C406C)
#define CCM_CCGR2 *((volatile unsigned int *)0X020C4070)
#define CCM_CCGR3 *((volatile unsigned int *)0X020C4074)
#define CCM_CCGR4 *((volatile unsigned int *)0X020C4078)
#define CCM_CCGR5 *((volatile unsigned int *)0X020C407C)
#define CCM_CCGR6 *((volatile unsigned int *)0X020C4080)
/*
* IOMUX 相关寄存器地址
*/
#define SW_MUX_GPIO1_IO03 *((volatile unsigned int *)0X020E0068)
#define SW_PAD_GPIO1_IO03 *((volatile unsigned int *)0X020E02F4)
/*
* GPIO1 相关寄存器地址
*/
#define GPIO1_DR *((volatile unsigned int *)0X0209C000)
#define GPIO1_GDIR *((volatile unsigned int *)0X0209C004)
#define GPIO1_PSR *((volatile unsigned int *)0X0209C008)
#define GPIO1_ICR1 *((volatile unsigned int *)0X0209C00C)
#define GPIO1_ICR2 *((volatile unsigned int *)0X0209C010)
#define GPIO1_IMR *((volatile unsigned int *)0X0209C014)
#define GPIO1_ISR *((volatile unsigned int *)0X0209C018)
#define GPIO1_EDGE_SEL *((volatile unsigned int *)0X0209C01C)
#endif #include "main.h"
/*
* @description : 使能I.MX6U所有外设时钟
* @param : 无
* @return : 无
*/
void clk_enable(void)
{
CCM_CCGR0 = 0xffffffff;
CCM_CCGR1 = 0xffffffff;
CCM_CCGR2 = 0xffffffff;
CCM_CCGR3 = 0xffffffff;
CCM_CCGR4 = 0xffffffff;
CCM_CCGR5 = 0xffffffff;
CCM_CCGR6 = 0xffffffff;
}
/*
* @description : 初始化LED对应的GPIO
* @param : 无
* @return : 无
*/
void led_init(void)
{
/* 1、初始化IO复用 */
SW_MUX_GPIO1_IO03 = 0x5; /* 复用为GPIO1_IO03 */
/* 2、、配置GPIO1_IO03的IO属性
*bit 16:0 HYS关闭
*bit [15:14]: 00 默认下拉
*bit [13]: 0 kepper功能
*bit [12]: 1 pull/keeper使能
*bit [11]: 0 关闭开路输出
*bit [7:6]: 10 速度100Mhz
*bit [5:3]: 110 R0/6驱动能力
*bit [0]: 0 低转换率
*/
SW_PAD_GPIO1_IO03 = 0X10B0;
/* 3、初始化GPIO */
GPIO1_GDIR = 0X0000008; /* GPIO1_IO03设置为输出 */
/* 4、设置GPIO1_IO03输出低电平，打开LED0 */
GPIO1_DR = 0X0;
}
/*
* @description : 打开LED灯
* @param : 无
* @return : 无
*/
void led_on(void)
{
/*
* 将GPIO1_DR的bit3清零
*/
GPIO1_DR &= ~(1<<3);
}
/*
* @description : 关闭LED灯
* @param : 无
* @return : 无
*/
void led_off(void)
{
/*
* 将GPIO1_DR的bit3置1
*/
GPIO1_DR |= (1<<3);
}
/*
* @description : 短时间延时函数
* @param - n : 要延时循环次数(空操作循环次数，模式延时)
* @return : 无
*/
void delay_short(volatile unsigned int n)
{
while(n--){}
}
/*
* @description : 延时函数,在396Mhz的主频下
* 延时时间大约为1ms
* @param - n : 要延时的ms数
* @return : 无
*/
void delay(volatile unsigned int n)
{
while(n--)
{
delay_short(0x7ff);
}
}
/*
* @description : mian函数
* @param : 无
* @return : 无
*/
int main(void)
{
clk_enable(); /* 使能所有的时钟 */
led_init(); /* 初始化led */
while(1) /* 死循环 */
{
led_off(); /* 关闭LED */
delay(500); /* 延时大约500ms */
led_on(); /* 打开LED */
delay(500); /* 延时大约500ms */
}
return 0;
}
3、编写链接脚本
链接脚本描述了要连接的文件，以及链接顺序，和链接首地址
SECTIONS{
. = 0x87800000;
.text :
{
start.o
*(.text)
}
.rodate ALIGN(4) : {*(.rodate)}
.date ALIGN(4) : {*(.date)}
__bss_start=.;
.bss ALIGN(4) : {*(.bss) *(COMMON)}
__bss_end=.;
}
二、 使用结构体(标准版)封装
1、C语言运行环境构建
start.s
.global _start /* 全局标号 */
.global _bss_start
_bss_start:
.word __bss_start
.global _bss_end
_bss_end:
.word __bss_end
/*
* 描述： _start函数，程序从此函数开始执行，此函数主要功能是设置C
* 运行环境。
*/
_start:
/* 进入SVC模式 */
mrs r0, cpsr
bic r0, r0, #0x1f /* 将r0寄存器中的低5位清零，也就是cpsr的M0~M4 */
orr r0, r0, #0x13 /* r0或上0x13,表示使用SVC模式 */
msr cpsr, r0 /* 将r0 的数据写入到cpsr_c中 */
/* 清BSS段 */
ldr r0, _bss_start
ldr r1, _bss_end
mov r2, #0
bss_loop:
stmia r0!, {r2} /* 向r0的地址写入0,然后r0寄存器保存的地址值加1 */
cmp r0, r1 /* 比较r0和r1，也就是__bss_start和__bss_end的值*/
ble bss_loop /* 如果小于等于的话就跳转到bss_loop继续清bss段*/
/* 设置sp指针 */
ldr sp,=0X80200000 /* 设置栈指针 */
b main /* 跳转到main函数 */
2、软件编写
imx6u.h
/*
* 外设寄存器组的基地址
*/
#define CCM_BASE (0X020C4000)
#define CCM_ANALOG_BASE (0X020C8000)
#define IOMUX_SW_MUX_BASE (0X020E0014)
#define IOMUX_SW_PAD_BASE (0X020E0204)
#define GPIO1_BASE (0x0209C000)
#define GPIO2_BASE (0x020A0000)
#define GPIO3_BASE (0x020A4000)
#define GPIO4_BASE (0x020A8000)
#define GPIO5_BASE (0x020AC000)
/*
* CCM寄存器结构体定义，分为CCM和CCM_ANALOG
*/
typedef struct
{
volatile unsigned int CCR;
volatile unsigned int CCDR;
volatile unsigned int CSR;
volatile unsigned int CCSR;
volatile unsigned int CACRR;
volatile unsigned int CBCDR;
volatile unsigned int CBCMR;
volatile unsigned int CSCMR1;
volatile unsigned int CSCMR2;
volatile unsigned int CSCDR1;
volatile unsigned int CS1CDR;
volatile unsigned int CS2CDR;
volatile unsigned int CDCDR;
volatile unsigned int CHSCCDR;
volatile unsigned int CSCDR2;
volatile unsigned int CSCDR3;
volatile unsigned int RESERVED_1[2];
volatile unsigned int CDHIPR;
volatile unsigned int RESERVED_2[2];
volatile unsigned int CLPCR;
volatile unsigned int CISR;
volatile unsigned int CIMR;
volatile unsigned int CCOSR;
volatile unsigned int CGPR;
volatile unsigned int CCGR0;
volatile unsigned int CCGR1;
volatile unsigned int CCGR2;
volatile unsigned int CCGR3;
volatile unsigned int CCGR4;
volatile unsigned int CCGR5;
volatile unsigned int CCGR6;
volatile unsigned int RESERVED_3[1];
volatile unsigned int CMEOR;
} CCM_Type;
typedef struct
{
volatile unsigned int PLL_ARM;
volatile unsigned int PLL_ARM_SET;
volatile unsigned int PLL_ARM_CLR;
volatile unsigned int PLL_ARM_TOG;
volatile unsigned int PLL_USB1;
volatile unsigned int PLL_USB1_SET;
volatile unsigned int PLL_USB1_CLR;
volatile unsigned int PLL_USB1_TOG;
volatile unsigned int PLL_USB2;
volatile unsigned int PLL_USB2_SET;
volatile unsigned int PLL_USB2_CLR;
volatile unsigned int PLL_USB2_TOG;
volatile unsigned int PLL_SYS;
volatile unsigned int PLL_SYS_SET;
volatile unsigned int PLL_SYS_CLR;
volatile unsigned int PLL_SYS_TOG;
volatile unsigned int PLL_SYS_SS;
volatile unsigned int RESERVED_1[3];
volatile unsigned int PLL_SYS_NUM;
volatile unsigned int RESERVED_2[3];
volatile unsigned int PLL_SYS_DENOM;
volatile unsigned int RESERVED_3[3];
volatile unsigned int PLL_AUDIO;
volatile unsigned int PLL_AUDIO_SET;
volatile unsigned int PLL_AUDIO_CLR;
volatile unsigned int PLL_AUDIO_TOG;
volatile unsigned int PLL_AUDIO_DENOM;
volatile unsigned int RESERVED_4[3];
volatile unsigned int PLL_VIDEO;
volatile unsigned int PLL_VIDEO_SET;
volatile unsigned int PLL_VIDEO_CLR;
volatile unsigned int PLL_VIDEO_TOG;
volatile unsigned int PLL_VIDEO_NUM;
volatile unsigned int RESERVED_5[3];
volatile unsigned int PLL_VIDEO_DENOM;
volatile unsigned int RESERVED_6[7];
volatile unsigned int PLL_ENET;
volatile unsigned int PLL_ENET_SET;
volatile unsigned int PLL_ENET_CLR;
volatile unsigned int PLL_ENET_TOG;
volatile unsigned int PFD_480;
volatile unsigned int PFD_480_SET;
volatile unsigned int PFD_480_CLR;
volatile unsigned int PFD_480_TOG;
volatile unsigned int PFD_528;
volatile unsigned int PFD_528_SET;
volatile unsigned int PFD_528_CLR;
volatile unsigned int PFD_528_TOG;
volatile unsigned int RESERVED_7[16];
volatile unsigned int MISC0;
volatile unsigned int MISC0_SET;
volatile unsigned int MISC0_CLR;
volatile unsigned int MISC0_TOG;
volatile unsigned int MISC1;
volatile unsigned int MISC1_SET;
volatile unsigned int MISC1_CLR;
volatile unsigned int MISC1_TOG;
volatile unsigned int MISC2;
volatile unsigned int MISC2_SET;
volatile unsigned int MISC2_CLR;
volatile unsigned int MISC2_TOG;
} CCM_ANALOG_Type;
/*
* IOMUX寄存器组
*/
typedef struct
{
volatile unsigned int BOOT_MODE0;
volatile unsigned int BOOT_MODE1;
volatile unsigned int SNVS_TAMPER0;
volatile unsigned int SNVS_TAMPER1;
volatile unsigned int SNVS_TAMPER2;
volatile unsigned int SNVS_TAMPER3;
volatile unsigned int SNVS_TAMPER4;
volatile unsigned int SNVS_TAMPER5;
volatile unsigned int SNVS_TAMPER6;
volatile unsigned int SNVS_TAMPER7;
volatile unsigned int SNVS_TAMPER8;
volatile unsigned int SNVS_TAMPER9;
volatile unsigned int JTAG_MOD;
volatile unsigned int JTAG_TMS;
volatile unsigned int JTAG_TDO;
volatile unsigned int JTAG_TDI;
volatile unsigned int JTAG_TCK;
volatile unsigned int JTAG_TRST_B;
volatile unsigned int GPIO1_IO00;
volatile unsigned int GPIO1_IO01;
volatile unsigned int GPIO1_IO02;
volatile unsigned int GPIO1_IO03;
volatile unsigned int GPIO1_IO04;
volatile unsigned int GPIO1_IO05;
volatile unsigned int GPIO1_IO06;
volatile unsigned int GPIO1_IO07;
volatile unsigned int GPIO1_IO08;
volatile unsigned int GPIO1_IO09;
volatile unsigned int UART1_TX_DATA;
volatile unsigned int UART1_RX_DATA;
volatile unsigned int UART1_CTS_B;
volatile unsigned int UART1_RTS_B;
volatile unsigned int UART2_TX_DATA;
volatile unsigned int UART2_RX_DATA;
volatile unsigned int UART2_CTS_B;
volatile unsigned int UART2_RTS_B;
volatile unsigned int UART3_TX_DATA;
volatile unsigned int UART3_RX_DATA;
volatile unsigned int UART3_CTS_B;
volatile unsigned int UART3_RTS_B;
volatile unsigned int UART4_TX_DATA;
volatile unsigned int UART4_RX_DATA;
volatile unsigned int UART5_TX_DATA;
volatile unsigned int UART5_RX_DATA;
volatile unsigned int ENET1_RX_DATA0;
volatile unsigned int ENET1_RX_DATA1;
volatile unsigned int ENET1_RX_EN;
volatile unsigned int ENET1_TX_DATA0;
volatile unsigned int ENET1_TX_DATA1;
volatile unsigned int ENET1_TX_EN;
volatile unsigned int ENET1_TX_CLK;
volatile unsigned int ENET1_RX_ER;
volatile unsigned int ENET2_RX_DATA0;
volatile unsigned int ENET2_RX_DATA1;
volatile unsigned int ENET2_RX_EN;
volatile unsigned int ENET2_TX_DATA0;
volatile unsigned int ENET2_TX_DATA1;
volatile unsigned int ENET2_TX_EN;
volatile unsigned int ENET2_TX_CLK;
volatile unsigned int ENET2_RX_ER;
volatile unsigned int LCD_CLK;
volatile unsigned int LCD_ENABLE;
volatile unsigned int LCD_HSYNC;
volatile unsigned int LCD_VSYNC;
volatile unsigned int LCD_RESET;
volatile unsigned int LCD_DATA00;
volatile unsigned int LCD_DATA01;
volatile unsigned int LCD_DATA02;
volatile unsigned int LCD_DATA03;
volatile unsigned int LCD_DATA04;
volatile unsigned int LCD_DATA05;
volatile unsigned int LCD_DATA06;
volatile unsigned int LCD_DATA07;
volatile unsigned int LCD_DATA08;
volatile unsigned int LCD_DATA09;
volatile unsigned int LCD_DATA10;
volatile unsigned int LCD_DATA11;
volatile unsigned int LCD_DATA12;
volatile unsigned int LCD_DATA13;
volatile unsigned int LCD_DATA14;
volatile unsigned int LCD_DATA15;
volatile unsigned int LCD_DATA16;
volatile unsigned int LCD_DATA17;
volatile unsigned int LCD_DATA18;
volatile unsigned int LCD_DATA19;
volatile unsigned int LCD_DATA20;
volatile unsigned int LCD_DATA21;
volatile unsigned int LCD_DATA22;
volatile unsigned int LCD_DATA23;
volatile unsigned int NAND_RE_B;
volatile unsigned int NAND_WE_B;
volatile unsigned int NAND_DATA00;
volatile unsigned int NAND_DATA01;
volatile unsigned int NAND_DATA02;
volatile unsigned int NAND_DATA03;
volatile unsigned int NAND_DATA04;
volatile unsigned int NAND_DATA05;
volatile unsigned int NAND_DATA06;
volatile unsigned int NAND_DATA07;
volatile unsigned int NAND_ALE;
volatile unsigned int NAND_WP_B;
volatile unsigned int NAND_READY_B;
volatile unsigned int NAND_CE0_B;
volatile unsigned int NAND_CE1_B;
volatile unsigned int NAND_CLE;
volatile unsigned int NAND_DQS;
volatile unsigned int SD1_CMD;
volatile unsigned int SD1_CLK;
volatile unsigned int SD1_DATA0;
volatile unsigned int SD1_DATA1;
volatile unsigned int SD1_DATA2;
volatile unsigned int SD1_DATA3;
volatile unsigned int CSI_MCLK;
volatile unsigned int CSI_PIXCLK;
volatile unsigned int CSI_VSYNC;
volatile unsigned int CSI_HSYNC;
volatile unsigned int CSI_DATA00;
volatile unsigned int CSI_DATA01;
volatile unsigned int CSI_DATA02;
volatile unsigned int CSI_DATA03;
volatile unsigned int CSI_DATA04;
volatile unsigned int CSI_DATA05;
volatile unsigned int CSI_DATA06;
volatile unsigned int CSI_DATA07;
}IOMUX_SW_MUX_Type;
typedef struct
{
volatile unsigned int DRAM_ADDR00;
volatile unsigned int DRAM_ADDR01;
volatile unsigned int DRAM_ADDR02;
volatile unsigned int DRAM_ADDR03;
volatile unsigned int DRAM_ADDR04;
volatile unsigned int DRAM_ADDR05;
volatile unsigned int DRAM_ADDR06;
volatile unsigned int DRAM_ADDR07;
volatile unsigned int DRAM_ADDR08;
volatile unsigned int DRAM_ADDR09;
volatile unsigned int DRAM_ADDR10;
volatile unsigned int DRAM_ADDR11;
volatile unsigned int DRAM_ADDR12;
volatile unsigned int DRAM_ADDR13;
volatile unsigned int DRAM_ADDR14;
volatile unsigned int DRAM_ADDR15;
volatile unsigned int DRAM_DQM0;
volatile unsigned int DRAM_DQM1;
volatile unsigned int DRAM_RAS_B;
volatile unsigned int DRAM_CAS_B;
volatile unsigned int DRAM_CS0_B;
volatile unsigned int DRAM_CS1_B;
volatile unsigned int DRAM_SDWE_B;
volatile unsigned int DRAM_ODT0;
volatile unsigned int DRAM_ODT1;
volatile unsigned int DRAM_SDBA0;
volatile unsigned int DRAM_SDBA1;
volatile unsigned int DRAM_SDBA2;
volatile unsigned int DRAM_SDCKE0;
volatile unsigned int DRAM_SDCKE1;
volatile unsigned int DRAM_SDCLK0_P;
volatile unsigned int DRAM_SDQS0_P;
volatile unsigned int DRAM_SDQS1_P;
volatile unsigned int DRAM_RESET;
volatile unsigned int TEST_MODE;
volatile unsigned int POR_B;
volatile unsigned int ONOFF;
volatile unsigned int SNVS_PMIC_ON_REQ;
volatile unsigned int CCM_PMIC_STBY_REQ;
volatile unsigned int BOOT_MODE0;
volatile unsigned int BOOT_MODE1;
volatile unsigned int SNVS_TAMPER0;
volatile unsigned int SNVS_TAMPER1;
volatile unsigned int SNVS_TAMPER2;
volatile unsigned int SNVS_TAMPER3;
volatile unsigned int SNVS_TAMPER4;
volatile unsigned int SNVS_TAMPER5;
volatile unsigned int SNVS_TAMPER6;
volatile unsigned int SNVS_TAMPER7;
volatile unsigned int SNVS_TAMPER8;
volatile unsigned int SNVS_TAMPER9;
volatile unsigned int JTAG_MOD;
volatile unsigned int JTAG_TMS;
volatile unsigned int JTAG_TDO;
volatile unsigned int JTAG_TDI;
volatile unsigned int JTAG_TCK;
volatile unsigned int JTAG_TRST_B;
volatile unsigned int GPIO1_IO00;
volatile unsigned int GPIO1_IO01;
volatile unsigned int GPIO1_IO02;
volatile unsigned int GPIO1_IO03;
volatile unsigned int GPIO1_IO04;
volatile unsigned int GPIO1_IO05;
volatile unsigned int GPIO1_IO06;
volatile unsigned int GPIO1_IO07;
volatile unsigned int GPIO1_IO08;
volatile unsigned int GPIO1_IO09;
volatile unsigned int UART1_TX_DATA;
volatile unsigned int UART1_RX_DATA;
volatile unsigned int UART1_CTS_B;
volatile unsigned int UART1_RTS_B;
volatile unsigned int UART2_TX_DATA;
volatile unsigned int UART2_RX_DATA;
volatile unsigned int UART2_CTS_B;
volatile unsigned int UART2_RTS_B;
volatile unsigned int UART3_TX_DATA;
volatile unsigned int UART3_RX_DATA;
volatile unsigned int UART3_CTS_B;
volatile unsigned int UART3_RTS_B;
volatile unsigned int UART4_TX_DATA;
volatile unsigned int UART4_RX_DATA;
volatile unsigned int UART5_TX_DATA;
volatile unsigned int UART5_RX_DATA;
volatile unsigned int ENET1_RX_DATA0;
volatile unsigned int ENET1_RX_DATA1;
volatile unsigned int ENET1_RX_EN;
volatile unsigned int ENET1_TX_DATA0;
volatile unsigned int ENET1_TX_DATA1;
volatile unsigned int ENET1_TX_EN;
volatile unsigned int ENET1_TX_CLK;
volatile unsigned int ENET1_RX_ER;
volatile unsigned int ENET2_RX_DATA0;
volatile unsigned int ENET2_RX_DATA1;
volatile unsigned int ENET2_RX_EN;
volatile unsigned int ENET2_TX_DATA0;
volatile unsigned int ENET2_TX_DATA1;
volatile unsigned int ENET2_TX_EN;
volatile unsigned int ENET2_TX_CLK;
volatile unsigned int ENET2_RX_ER;
volatile unsigned int LCD_CLK;
volatile unsigned int LCD_ENABLE;
volatile unsigned int LCD_HSYNC;
volatile unsigned int LCD_VSYNC;
volatile unsigned int LCD_RESET;
volatile unsigned int LCD_DATA00;
volatile unsigned int LCD_DATA01;
volatile unsigned int LCD_DATA02;
volatile unsigned int LCD_DATA03;
volatile unsigned int LCD_DATA04;
volatile unsigned int LCD_DATA05;
volatile unsigned int LCD_DATA06;
volatile unsigned int LCD_DATA07;
volatile unsigned int LCD_DATA08;
volatile unsigned int LCD_DATA09;
volatile unsigned int LCD_DATA10;
volatile unsigned int LCD_DATA11;
volatile unsigned int LCD_DATA12;
volatile unsigned int LCD_DATA13;
volatile unsigned int LCD_DATA14;
volatile unsigned int LCD_DATA15;
volatile unsigned int LCD_DATA16;
volatile unsigned int LCD_DATA17;
volatile unsigned int LCD_DATA18;
volatile unsigned int LCD_DATA19;
volatile unsigned int LCD_DATA20;
volatile unsigned int LCD_DATA21;
volatile unsigned int LCD_DATA22;
volatile unsigned int LCD_DATA23;
volatile unsigned int NAND_RE_B;
volatile unsigned int NAND_WE_B;
volatile unsigned int NAND_DATA00;
volatile unsigned int NAND_DATA01;
volatile unsigned int NAND_DATA02;
volatile unsigned int NAND_DATA03;
volatile unsigned int NAND_DATA04;
volatile unsigned int NAND_DATA05;
volatile unsigned int NAND_DATA06;
volatile unsigned int NAND_DATA07;
volatile unsigned int NAND_ALE;
volatile unsigned int NAND_WP_B;
volatile unsigned int NAND_READY_B;
volatile unsigned int NAND_CE0_B;
volatile unsigned int NAND_CE1_B;
volatile unsigned int NAND_CLE;
volatile unsigned int NAND_DQS;
volatile unsigned int SD1_CMD;
volatile unsigned int SD1_CLK;
volatile unsigned int SD1_DATA0;
volatile unsigned int SD1_DATA1;
volatile unsigned int SD1_DATA2;
volatile unsigned int SD1_DATA3;
volatile unsigned int CSI_MCLK;
volatile unsigned int CSI_PIXCLK;
volatile unsigned int CSI_VSYNC;
volatile unsigned int CSI_HSYNC;
volatile unsigned int CSI_DATA00;
volatile unsigned int CSI_DATA01;
volatile unsigned int CSI_DATA02;
volatile unsigned int CSI_DATA03;
volatile unsigned int CSI_DATA04;
volatile unsigned int CSI_DATA05;
volatile unsigned int CSI_DATA06;
volatile unsigned int CSI_DATA07;
volatile unsigned int GRP_ADDDS;
volatile unsigned int GRP_DDRMODE_CTL;
volatile unsigned int GRP_B0DS;
volatile unsigned int GRP_DDRPK;
volatile unsigned int GRP_CTLDS;
volatile unsigned int GRP_B1DS;
volatile unsigned int GRP_DDRHYS;
volatile unsigned int GRP_DDRPKE;
volatile unsigned int GRP_DDRMODE;
volatile unsigned int GRP_DDR_TYPE;
}IOMUX_SW_PAD_Type;
/*
* GPIO寄存器结构体
*/
typedef struct
{
volatile unsigned int DR;
volatile unsigned int GDIR;
volatile unsigned int PSR;
volatile unsigned int ICR1;
volatile unsigned int ICR2;
volatile unsigned int IMR;
volatile unsigned int ISR;
volatile unsigned int EDGE_SEL;
}GPIO_Type;
/*
* 外设指针
*/
#define CCM ((CCM_Type *)CCM_BASE)
#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
#define IOMUX_SW_MUX ((IOMUX_SW_MUX_Type *)IOMUX_SW_MUX_BASE)
#define IOMUX_SW_PAD ((IOMUX_SW_PAD_Type *)IOMUX_SW_PAD_BASE)
#define GPIO1 ((GPIO_Type *)GPIO1_BASE)
#define GPIO2 ((GPIO_Type *)GPIO2_BASE)
#define GPIO3 ((GPIO_Type *)GPIO3_BASE)
#define GPIO4 ((GPIO_Type *)GPIO4_BASE)
#define GPIO5 ((GPIO_Type *)GPIO5_BASE)main.c
#include "imx6u.h"
/*
* @description : 使能I.MX6U所有外设时钟
* @param : 无
* @return : 无
*/
void clk_enable(void)
{
CCM->CCGR0 = 0XFFFFFFFF;
CCM->CCGR1 = 0XFFFFFFFF;
CCM->CCGR2 = 0XFFFFFFFF;
CCM->CCGR3 = 0XFFFFFFFF;
CCM->CCGR4 = 0XFFFFFFFF;
CCM->CCGR5 = 0XFFFFFFFF;
CCM->CCGR6 = 0XFFFFFFFF;
}
/*
* @description : 初始化LED对应的GPIO
* @param : 无
* @return : 无
*/
void led_init(void)
{
/* 1、初始化IO复用 */
IOMUX_SW_MUX->GPIO1_IO03 = 0X5; /* 复用为GPIO1_IO03 */
/* 2、配置GPIO1_IO03的IO属性
*bit 16:0 HYS关闭
*bit [15:14]: 00 默认下拉
*bit [13]: 0 kepper功能
*bit [12]: 1 pull/keeper使能
*bit [11]: 0 关闭开路输出
*bit [7:6]: 10 速度100Mhz
*bit [5:3]: 110 R0/6驱动能力
*bit [0]: 0 低转换率
*/
IOMUX_SW_PAD->GPIO1_IO03 = 0X10B0;
/* 3、初始化GPIO */
GPIO1->GDIR = 0X0000008; /* GPIO1_IO03设置为输出 */
/* 4、设置GPIO1_IO03输出低电平，打开LED0 */
GPIO1->DR &= ~(1 << 3);
}
/*
* @description : 打开LED灯
* @param : 无
* @return : 无
*/
void led_on(void)
{
/* 将GPIO1_DR的bit3清零 */
GPIO1->DR &= ~(1<<3);
}
/*
* @description : 关闭LED灯
* @param : 无
* @return : 无
*/
void led_off(void)
{
/* 将GPIO1_DR的bit3置1 */
GPIO1->DR |= (1<<3);
}
/*
* @description : 短时间延时函数
* @param - n : 要延时循环次数(空操作循环次数，模式延时)
* @return : 无
*/
void delay_short(volatile unsigned int n)
{
while(n--){}
}
/*
* @description : 延时函数,在396Mhz的主频下
* 延时时间大约为1ms
* @param - n : 要延时的ms数
* @return : 无
*/
void delay(volatile unsigned int n)
{
while(n--)
{
delay_short(0x7ff);
}
}
/*
* @description : mian函数
* @param : 无
* @return : 无
*/
int main(void)
{
clk_enable(); /* 使能所有的时钟 */
led_init(); /* 初始化led */
while(1) /* 死循环 */
{
led_off(); /* 关闭LED */
delay(500); /* 延时500ms */
led_on(); /* 打开LED */
delay(500); /* 延时500ms */
}
return 0;
}
3、编写链接脚本
imx6ul.lds
SECTIONS{
. = 0X87800000;
.text :
{
start.o
*(.text)
}
.rodata ALIGN(4) : {*(.rodata*)}
.data ALIGN(4) : { *(.data) }
__bss_start = .;
.bss ALIGN(4) : { *(.bss) *(COMMON) }
__bss_end = .;
}Makefile
objs := start.o main.o
ledc.bin:$(objs)
arm-linux-gnueabihf-ld -Timx6ul.lds -o ledc.elf $^
arm-linux-gnueabihf-objcopy -O binary -S ledc.elf $@
arm-linux-gnueabihf-objdump -D -m arm ledc.elf > ledc.dis
%.o:%.s
arm-linux-gnueabihf-gcc -Wall -nostdlib -c -O2 -o $@ $<
%.o:%.S
arm-linux-gnueabihf-gcc -Wall -nostdlib -c -O2 -o $@ $<
%.o:%.c
arm-linux-gnueabihf-gcc -Wall -nostdlib -c -O2 -o $@ $<
clean:
rm -rf *.o ledc.bin ledc.elf ledc.dis
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