Behavioral Simulation,Structural Simulation,Timing Simulation

Behavioral simulation employs a high level of abstraction to modelthe design. A behavioral design might, for example, contain high-leveloperations, such as a four-bit addition operator (this is not an adder,as in a structural design), without containing specifics on how thedesign will be implemented. Synthesis tools then take these behavioraldesigns and infer the actual gate structures and connections to beused, generating a netlist description.

Behavioral simulation is performed using a pre-synthesis Hardware Description Language (HDL) descriptionof the design. Of the three simulation methods (behavioral, structural,and timing), behavioral simulation runs the fastest but provides theleast design information.

Behavioral simulation allows you to verify syntax and functionalitywithout timing information. During design development, most verificationis accomplished through behavioral simulation. Errors identified earlyin the design cycle are inexpensive to fix compared to functionalerrors identified during silicon debug. After the required functionalityis achieved, structural and timing simulation methods can be implementedto obtain more detailed verification data.

The tools create structural simulation files from a design thathas already been synthesized. The resulting model does not includeany behavioral constructs and is a purely structural description ofthe design. At this point, you can verify what the synthesis tooldid with the behavioral design. The post-synthesized structural simulationis a functional simulation that allows you to identify initializationissues and to analyze "don’t care" conditions. Timing informationis not used at this simulation level. Compared with behavioral simulation,structural simulation runs somewhat slowly but provides more detail.

Xilinx® tools have the ability to write out purely structural Hardware Description Language (HDL) netlists for a post-synthesized design. These VHDL or Verilognetlists are written using UNISIM library components, which describeall the low-level hardware primitives available in Xilinx FPGAs.

Timing simulation includes back-annotated timing information butis otherwise similar to structural simulation. Timingsimulation is important in verifying the operation of your circuitafter the worst-case place and route (PAR) delays are calculated foryour design. The back annotation process produces a netlist of librarycomponents annotated in a Standard Delay Format (SDF) file with the appropriate block andnet delays from the place and route process. The simulation identifiesany race conditions and setup-and-hold violations based on the operatingconditions for the specified functionality. Timing simulation takeslonger to run and provides more detail than either the behavioralor structural simulation methods.