ARM之IIC总线英文手册笔记

Dedicated 专用的
Initiate 开始/启动(搭配信号)
Terminate 结束
Arbitration 仲裁
Transition 转变/过度
Generated 产生
Unlimitedly 无限的
Prescaler 预定标
Comparator 比较器
Inactive 空闲的
Format 格式
Pulse 脉冲
Notify 通告
Performed 执行
resume. 继续
contention 斗争
FLOWCHARTS 流程图

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I2C总线标准英文版V2.1,可以和中文版对照着看,目录如下 1 PREFACE. . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Version 1.0 - 1992. . . . . . . . . . . . . . . . . . . . 3 1.2 Version 2.0 - 198. . . . . . . . . . . . . . . . . . . . . 3 1.3 Version 2.1 - 1999. . . . . . . . . . . . . . . . . . . . 3 1.4 Purchase of Philips I2C-bus components . . 3 2 THE I2C-BUS BENEFITS DESIGNERS AND MANUFACTURERS. . . . . . . . . . . . . . .4 2.1 Designer benefits . . . . . . . . . . . . . . . . . . . . 4 2.2 Manufacturer benefits . . . . . . . . . . . . . . . . . 6 3 INTRODUCTION TO THE I2C-BUS SPECIFICATION . . . . . . . . . . . . . . . . . . . . .6 4 THE I2C-BUS CONCEPT . . . . . . . . . . . . . . .6 5 GENERAL CHARACTERISTICS . . . . . . . . .8 6 BIT TRANSFER . . . . . . . . . . . . . . . . . . . . . .8 6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 START and STOP conditions . . . . . . . . . . . 9 7 TRANSFERRING DATA . . . . . . . . . . . . . . .10 7.1 Byte format . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2 Acknowledge. . . . . . . . . . . . . . . . . . . . . . . 10 8 ARBITRATION AND CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . .11 8.1 Synchronization . . . . . . . . . . . . . . . . . . . . 11 8.2 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3 Use of the clock synchronizing mechanism as a handshake . . . . . . . . . . . 13 9 FORMATS WITH 7-BIT ADDRESSES . . . .13 10 7-BIT ADDRESSING . . . . . . . . . . . . . . . . .15 10.1 Definition of bits in the first byte . . . . . . . . 15 10.1.1 General call address . . . . . . . . . . . . . . . . . 16 10.1.2 START byte . . . . . . . . . . . . . . . . . . . . . . . 17 10.1.3 CBUS compatibility . . . . . . . . . . . . . . . . . . 18 11 EXTENSIONS TO THE STANDARDMODE I2C-BUS SPECIFICATION . . . . . . .19 12 FAST-MODE. . . . . . . . . . . . . . . . . . . . . . . .19 13 Hs-MODE . . . . . . . . . . . . . . . . . . . . . . . . . .20 13.1 High speed transfer. . . . . . . . . . . . . . . . . . 20 13.2 Serial data transfer format in Hs-mode . . . 21 13.3 Switching from F/S- to Hs-mode and back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 13.4 Hs-mode devices at lower speed modes. . 24 13.5 Mixed speed modes on one serial bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13.5.1 F/S-mode transfer in a mixed-speed bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.5.2 Hs-mode transfer in a mixed-speed bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.5.3 Timing requirements for the bridge in a mixed-speed bus system. . . . . . . . . . . . . . 27 14 10-BIT ADDRESSING . . . . . . . . . . . . . . . . 27 14.1 Definition of bits in the first two bytes. . . . . 27 14.2 Formats with 10-bit addresses. . . . . . . . . . 27 14.3 General call address and start byte with 10-bit addressing . . . . . . . . . . . . . . . . . . . . 30 15 ELECTRICAL SPECIFICATIONS AND TIMING FOR I/O STAGES AND BUS LINES . . . . . . . . . . . . . . . . . . . . 30 15.1 Standard- and Fast-mode devices. . . . . . . 30 15.2 Hs-mode devices . . . . . . . . . . . . . . . . . . . . 34 16 ELECTRICAL CONNECTIONS OF I2C-BUS DEVICES TO THE BUS LINES . 37 16.1 Maximum and minimum values of resistors Rp and Rs for Standard-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 39 17 APPLICATION INFORMATION. . . . . . . . . 41 17.1 Slope-controlled output stages of Fast-mode I2C-bus devices . . . . . . . . . . . . 41 17.2 Switched pull-up circuit for Fast-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 41 17.3 Wiring pattern of the bus lines . . . . . . . . . . 42 17.4 Maximum and minimum values of resistors Rp and Rs for Fast-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 42 17.5 Maximum and minimum values of resistors Rp and Rs for Hs-mode I2C-bus devices . . . . . . . . . . . . . . . . . . . . . 42 18 BI-DIRECTIONAL LEVEL SHIFTER FOR F/S-MODE I2C-BUS SYSTEMS . . . . 42 18.1 Connecting devices with different logic levels . . . . . . . . . . . . . . . . . . . . . . . . . 43 18.1.1 Operation of the level shifter . . . . . . . . . . . 44 19 DEVELOPMENT TOOLS AVAILABLE FROM PHILIPS . . . . . . . . . . . . . . . . . . . . . 45 20 SUPPORT LITERATURE . . . . . . . . . . . . . 46
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