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原创 Verilog variable select group of bits from a vector
Verilog-2001 adds the capability to use variables to select a group of bits from a vector. ◆ The starting point of the part-select can vary. ◆ The width of the part-select remains constant. reg
2017-08-30 15:02:39 277
翻译 Difference between physically exclusive,logically exclusive and async clock groups
physically_exclusive: Means Timing paths between these clock domains are false, but only one clock can exist in the design at the same time. ETS/Tempus will filter out the SI interactions of nets
2017-07-11 10:31:02 3739
SystemC 2.0 User's Guide
2009-08-11
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