Verilog variable select group of bits from a vector

Verilog-2001 adds the capability to use variables to select a group of bits from a vector.

◆ The starting point of the part-select can vary.

◆ The width of the part-select remains constant.

reg [63:0] word;

reg [3:0] byte_num; //a value from 0 to 7

wire [7:0] byteN = word[byte_num*8 +: 8];

The byte_num*8 is the starting point of the part-select.

Constant 8 is the width of the part-select.

+: indicates the part-select increases from the starting point.

-: indicates the part-select decreases from the starting point.

Example:

1)

reg [1023:0] a;

reg [7:0] shift;

wire [9:0] shift_number;

always @ (*) begin : shift_proc
    integer i;
    shift = 8'h0;
    for (i=0; i<=1016; i++) begin
        if(i == shift_number[9:0])
            shift = a[i+:8];
    end
end

2)

reg [1023:0] a;

reg [7:0] shift;

wire [9:0] shift_number;

always @ (*) begin : shift_proc
    integer i;
    shift = 8'h0;
    for (i=7; i<=1023; i++) begin
        if(i-7 == shift_number[9:0])
            shift = a[i-:8];
    end
end