xilinx官方提供的spartan 3 starter kit有两片ISSI 256Kx16位的SRAM,这两个SRAM复用地址线,数据线都引入到FPGA,因此,FPGA访问外部SRAM的位宽是32位,基于该开发板,使用XPS设计嵌入式系统使用xilinx默认的配置32位宽。但是对于某些应用,fpga引脚是稀缺资源,因此32位宽不可能实现,此时需要使用8位或者16为的SRAM(ISSI提供8、16、32位的高速异步SRAM芯片)。本文阐述了,使用emc ip core连接16位SRAM的例子。本文只使用开发板上两片SRAM中的一片(IC11)。
system.mhs
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
# Sun Dec 14 15:48:49 2008
# Target Board: Xilinx Spartan-3 Starter Board Rev E
# Family: spartan3
# Device: XC3S200
# Package: FT256
# Speed Grade: -4
# Processor: microblaze_0
# System clock frequency: 50.00 MHz
# On Chip Memory : 8 KB
# Total Off Chip Memory : 1 MB
# - SRAM = 1 MB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A, DIR = O, VEC = [13:30]
PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ, DIR = IO, VEC = [0:15]
PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN, DIR = O, VEC = [0:0]
PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN, DIR = O, VEC = [0:0]
PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN, DIR = O
PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN, DIR = O, VEC = [0:1]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0