《CSAPP》（第3版）答案（第四章）

《CSAPP》（第3版）答案（第四章）

P45

• A
  不。if REG is %rsp, we push %rsp-8 instead of %rsp into stack如果REG是%rsp，那么入栈的是%rsp-8而不是%rsp。
• B
  movq REG, -8(%rsp)
  subq $8, %rsp

P46

• A
  不是。如果REG是%rsp， movq (%rsp), REG 将右边的值弹出到%esp中， 但是 addq $8, %rsp 改变了它的值
• B
  addq $8, %rsp
  movq 8(%rsp), REG

P47

• A

#include <stdio.h>
void bubble_ptr(long* data,long count){
   
    long *i,*last;
    for (last = data+count-1;last>data;last--){
   
        for (i=data;i<last;i++){
   
            if(*(i+1)<*i){
   
                long t = *(i+1);
                *(i+1) = *i;
                *i = t;
            }
        }
    }
}
int main(){
   
    long ass[4] = {
   1,8,4,0};
    bubble_ptr(ass,4);
    for(int i=0;i<4;i++)
        printf("%d ",ass[i]);
}

• B
  Sorry.

.pos 0
 irmovq stack, %rsp
 call main
 halt
 
# Array of 4 elements
.align 8
data:
  .quad 0x0000000000000004
  .quad 0x0000000000000003
  .quad 0x0000000000000002
data_end:
  .quad 0x0000000000000001
main:
  irmovq data,%rdi
 irmovq data_end,%rsi
 call ysBubbleP
 ret
# long ys_bubble_p(long *data, long *end)
# data in %rdi, end in %rsi
ysBubbleP:
  jmp L2
L4:
  mrmovq 8(%rax), %r9
  mrmovq (%rax), %r10
  rrmovq %r9, %r8
  subq %r10, %r8
  jge L3
  rmmovq %r10, 8(%rax)
  rmmovq %r9, (%rax)
L3:
  irmovq $8, %r8
  addq %r8, %rax
  jmp L5
L6:
  rrmovq %rdi, %rax
L5:
  rrmovq %rsi, %r8
  subq %rax, %r8
  jg L4
  irmovq $8, %r8
  subq %r8, %rsi
L2:
  rrmovq %rsi, %r8
  subq %rdi, %r8
  jg L6
 ret
.pos 0x200
stack:

P48

Sorry.

.pos 0
 irmovq stack, %rsp
 call main
 halt
# Array of 4 elements
.align 8
data:
  .quad 0x0000000000000004
  .quad 0x0000000000000003
  .quad 0x0000000000000002
data_end:
  .quad 0x0000000000000001
main:
  irmovq data,%rdi
 irmovq data_end,%rsi
 call ysBubbleP
 ret
# long ys_bubble_p(long *data, long *end)
# data in %rdi, end in %rsi
ysBubbleP:
  jmp L2
L4:
  mrmovq 8(%rax), %r9
  mrmovq (%rax), %r10
  rrmovq %r9, %r8
  subq %r10, %r8
##############################################################
# begin differences
##############################################################
  cmovl %r9, %r11
  cmovl %r10, %r9
  cmovl %r11, %r10
  rmmovq %r9, 8(%rax)
  rmmovq %r10, (%rax)
##############################################################
# end
##############################################################
  irmovq $8, %r8
  addq %r8, %rax
  jmp L5
L6:
  rrmovq %rdi, %rax
L5:
  rrmovq %rsi, %r8
  subq %rax, %r8
  jg L4
  irmovq $8, %r8
  subq %r8, %rsi
L2:
  rrmovq %rsi, %r8
  subq %rdi, %r8
  jg L6
 ret
.pos 0x200
stack:

P49

注意，三个$xor$等价于一次交换，即：
x=x^y;
y=x^y;
x=x^y;所以：

.pos 0
 irmovq stack, %rsp
 call main
 halt
 
# Array of 4 elements
.align 8
data:
  .quad 0x0000000000000004
  .quad 0x0000000000000003
  .quad 0x0000000000000002
data_end:
  .quad 0x0000000000000001
  
main:
  irmovq data,%rdi
 irmovq data_end,%rsi
 call ysBubbleP
 ret
# long ys_bubble_p(long *data, long *end)
# data in %rdi, end in %rsi
ysBubbleP:
  jmp L2
L4:
  mrmovq 8(%rax), %r9
  mrmovq (%rax), %r10
############################################
# begin differences
############################################
  rrmovq %r9, %r8
  rrmovq %r10, %r11
  xorq %r9, %r10
  subq %r11, %r8
  cmovge %r11, %r9
  xorq %r10, %r9
  xorq %r9, %r10
  rmmovq %r9, 8(%rax)
  rmmovq %r10, (%rax)
############################################
# end
############################################
  irmovq $8, %r8
  addq %r8, %rax
  jmp L5
L6:
  rrmovq %rdi, %rax
L5:
  rrmovq %rsi, %r8
  subq %rax, %r8
  jg L4
  irmovq $8, %r8
  subq %r8, %rsi
L2:
  rrmovq %rsi, %r8
  subq %rdi, %r8
  jg L6

 ret
.pos 0x200
stack:

P50

.pos 0
 irmovq stack, %rsp
 call main
 halt
 
# Array of 4 elements
.align 8
array:
  .quad 0x0000000000000000
  .quad 0x0000000000000000
  .quad 0x0000000000000000
  .quad 0x0000000000000000
  
main:
  # test number 1, -1, 3, 5
  irmovq array, %r10
  irmovq $1,%rdi
 call switchv
  rmmovq %rax, (%r10)
  irmovq $-1,%rdi
 call switchv
  rmmovq %rax, 8(%r10)
  irmovq $3,%rdi
 call switchv
  rmmovq %rax, 16(%r10)
  irmovq $5,%rdi
 call switchv
  rmmovq %rax, 24(%r10)
 ret
table:
  .quad LD  # default branch
  .quad L0  # idx == 0
  .quad L1  # idx == 1
  .quad L2  # idx == 2
  .quad L3  # idx == 3
  .quad L4  # idx == 4
  .quad L5  # idx == 5
# long switchv(long idx)
# idx in %rdi
switchv:
  # contant number
  irmovq $8, %r8
  irmovq $0, %r10
  irmovq $1, %r11
  irmovq $0, %rax
  irmovq table, %rcx # table address
  rrmovq %rdi, %rdx
  subq %r8, %rdx
  jg def     # idx > 5
  subq %r10, %rdi
  jl def     # idx < 0
mul: # calculate 8 * %rdi
  subq %r10, %rdi
  je addr
  addq %r8, %rcx
  subq %r11, %rdi
  jmp mul
addr: # jump using table address
  addq %r8, %rcx
  mrmovq (%rcx), %rdi
  pushq %rdi
  ret
def: # default branch
  irmovq table, %rcx
  mrmovq (%rcx), %rdi
  pushq %rdi
  ret
L0:
  irmovq $0xaaa, %rax
  ret
L1:
  jmp LD
L2:
  jmp L5
L3:
  irmovq $0xccc, %rax
  ret
L4:
  jmp LD
L5:
  irmovq $0xbbb, %rax
  ret
LD:
  irmovq $0xddd, %rax
  
  ret
.pos 0x200
stack:

P51

phase	iaddq V,rB
Fetch	icode:ifun = M1[PC]; rA:rB = M1[PC+1]; valC = M8[PC+2]; valP = PC + 10;
Decode	valB = R[rB]
Execute	valE = valB + valC; set CC
Memory	-
Writeback	R[rB] = valE
PC	PC = valP

P52

#/* $begin seq-all-hcl */
####################################################################
#  HCL Description of Control for Single Cycle Y86-64 Processor SEQ   #
#  Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2010       #
####################################################################

## Your task is to implement the iaddq instruction
## The file contains a declaration of the icodes
## for iaddq (IIADDQ)
## Your job is to add the rest of the logic to make it work

####################################################################
#    C Include's.  Don't alter these                               #
####################################################################

quote '#include <stdio.h>'
quote '#include "isa.h"'
quote '#include "sim.h"'
quote 'int sim_main(int argc, char *argv[]);'
quote 'word_t gen_pc(){return 0;}'
quote 'int main(int argc, char *argv[])'
quote '  {plusmode=0;return sim_main(argc,argv);}'

####################################################################
#    Declarations.  Do not change/remove/delete any of these       #
####################################################################

##### Symbolic representation of Y86-64 Instruction Codes #############
wordsig INOP  'I_NOP'
wordsig IHALT 'I_HALT'
wordsig IRRMOVQ 'I_RRMOVQ'
wordsig IIRMOVQ 'I_IRMOVQ'
wordsig IRMMOVQ 'I_RMMOVQ'
wordsig IMRMOVQ 'I_MRMOVQ'
wordsig IOPQ 'I_ALU'
wordsig IJXX 'I_JMP'
wordsig ICALL 'I_CALL'
wordsig IRET 'I_RET'
wordsig IPUSHQ 'I_PUSHQ'
wordsig IPOPQ 'I_POPQ'

# Instruction code for iaddq instruction
wordsig IIADDQ 'I_IADDQ'

##### Symbolic represenations of Y86-64 function codes                  #####
wordsig FNONE    'F_NONE'        # Default function code

##### Symbolic representation of Y86-64 Registers referenced explicitly #####
wordsig RRSP     'REG_RSP'     # Stack Pointer
wordsig RNONE    'REG_NONE'    # Special value indicating "no register"

##### ALU Functions referenced explicitly                            #####
wordsig ALUADD 'A_ADD'  # ALU should add its arguments

##### Possible instruction status values                             #####
wordsig SAOK 'STAT_AOK' # Normal execution
wordsig SADR 'STAT_ADR' # Invalid memory address
wordsig SINS 'STAT_INS' # Invalid instruction
wordsig SHLT 'STAT_HLT' # Halt instruction encountered

##### Signals that can be referenced by control logic ####################

##### Fetch stage inputs  #####
wordsig pc 'pc'    # Program counter
##### Fetch stage computations  #####
wordsig imem_icode 'imem_icode'  # icode field from instruction memory
wordsig imem_ifun  'imem_ifun'   # ifun field from instruction memory
wordsig icode   'icode'  # Instruction control code
wordsig ifun   'ifun'  # Instruction function
wordsig rA   'ra'   # rA field from instruction
wordsig rB   'rb'   # rB field from instruction
wordsig valC   'valc'  # Constant from instruction
wordsig valP   'valp'  # Address of following instruction
boolsig imem_error 'imem_error'  # Error signal from instruction memory
boolsig instr_valid 'instr_valid' # Is fetched instruction valid?

##### Decode stage computations  #####
wordsig valA 'vala'   # Value from register A port
wordsig valB 'valb'   # Value from register B port

##### Execute stage computations #####
wordsig valE 'vale'   # Value computed by ALU
boolsig Cnd 'cond'   # Branch test

##### Memory stage computations  #####
wordsig valM 'valm'   # Value read from memory
boolsig dmem_error 'dmem_error'  # Error signal from data memory

####################################################################
#    Control Signal Definitions.                                   #
####################################################################

################ Fetch Stage     ###################################

# Determine instruction code
word icode = [
 imem_error: INOP;
 1: imem_icode;  # Default: get from instruction memory
];

# Determine instruction function
word ifun = [
 imem_error: FNONE;
 1: imem_ifun;  # Default: get from instruction memory
];

bool instr_valid = icode in
 {
    INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,
        IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ, IIADDQ };

# Does fetched instruction require a regid byte?
bool need_regids =
 icode in {
    IRRMOVQ, IOPQ, IPUSHQ, IPOPQ, 
       IIRMOVQ, IRMMOVQ, IMRMOVQ, IIADDQ };

# Does fetched instruction require a constant word?
bool need_valC =
 icode in {
    IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL, IIADDQ };

################ Decode Stage    ###################################

## What register should be used as the A source?
word srcA = [
 icode in {
    IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ  } : rA;
 icode in {
    IPOPQ, IRET } : RRSP;
 1 : RNONE; # Don't need register
];

## What register should be used as the B source?
word srcB = [
 icode in {
    IOPQ, IRMMOVQ, IMRMOVQ, IIADDQ } : rB;
 icode in {
    IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;
 1 : RNONE;  # Don't need register
];

## What register should be used as the E destination?
word dstE = [
 icode in {
    IRRMOVQ } && Cnd : rB;
 icode in {
    IIRMOVQ, IOPQ, IIADDQ } : rB;
 icode in {
    IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;
 1 : RNONE;  # Don't write any register
];

## What register should be used as the M destination?
word dstM = [
 icode in {
    IMRMOVQ, IPOPQ } : rA;
 1 : RNONE;  # Don't write any register
];

################ Execute Stage   ###################################

## Select input A to ALU

word aluA = [
 icode in {
    IRRMOVQ, IOPQ } : valA;
 icode in {
    IIRMOVQ, IRMMOVQ, IMRMOVQ, IIADDQ } : valC;
 icode in {
    ICALL, IPUSHQ } : -8;
 icode in {
    IRET, IPOPQ } : 8;
 # Other instructions don't need ALU
];

## Select input B to ALU

word aluB = [
 icode in {
    IRMMOVQ, IMRMOVQ, IOPQ, ICALL,
        IPUSHQ, IRET, IPOPQ, IIADDQ } : valB;
 icode in {
    IRRMOVQ, IIRMOVQ } : 0;
 # Other instructions don't need ALU
];

## Set the ALU function

word alufun = [
 icode == IOPQ : ifun;
 1 : ALUADD;
];

## Should the condition codes be updated?

bool set_cc = icode in {
    IOPQ, IIADDQ };

################ Memory Stage    ###################################

## Set read control signal
bool mem_read = icode in {
    IMRMOVQ, IPOPQ, IRET };
## Set write control signal
bool mem_write = icode in {
    IRMMOVQ, IPUSHQ, ICALL };
## Select memory address
word mem_addr = [
 icode in {
    IRMMOVQ, IPUSHQ, ICALL, IMRMOVQ } : valE;
 icode in {
    IPOPQ, IRET } : valA;
 # Other instructions don't need address
];
## Select memory input data
word mem_data = [
 # Value from register
 icode in {
    IRMMOVQ, IPUSHQ } : valA;
 # Return PC
 icode == ICALL : valP;
 # Default: Don't write anything
];
## Determine instruction status
word Stat = [
 imem_error || dmem_error : SADR;
 !instr_valid: SINS;
 icode == IHALT : SHLT;
 1 : SAOK;
];
################ Program Counter Update ############################
## What address should instruction be fetched at
word new_pc = [
 # Call.  Use instruction constant
 icode == ICALL : valC;
 # Taken branch.  Use instruction constant
 icode == IJXX && Cnd : valC;
 # Completion of RET instruction.  Use value from stack
 icode == IRET : valM;
 # Default: Use incremented PC
 1 : valP;
];
#/* $end seq-all-hcl */

P53

#/* $begin pipe-stall-hcl */
####################################################################
#    HCL Description of Control for Pipelined Y86-64 Processor     #
#    Copyright (C) Randal E. Bryant, David R. O'Hallaron, 2014     #
####################################################################
## Your task is to make the pipeline work without using any forwarding
## The normal bypassing logic in the file is disabled.
## You can only change the pipeline control logic at the end of this file.
## The trick is to make the pipeline stall whenever there is a data hazard.
####################################################################
#    C Include's.  Don't alter these                               #
####################################################################
quote '#include <stdio.h>'
quote '#include "isa.h"'
quote '#include "pipeline.h"'
quote '#include "stages.h"'
quote '#include "sim.h"'
quote 'int sim_main(int argc, char *argv[]);'
quote 'int main(int argc, char *argv[]){return sim_main(argc,argv);}'
####################################################################
#    Declarations.  Do not change/remove/delete any of these       #
####################################################################
##### Symbolic representation of Y86-64 Instruction Codes #############
wordsig INOP  'I_NOP'
wordsig IHALT 'I_HALT'
wordsig IRRMOVQ 'I_RRMOVQ'
wordsig IIRMOVQ 'I_IRMOVQ'
wordsig IRMMOVQ 'I_RMMOVQ'
wordsig IMRMOVQ 'I_MRMOVQ'
wordsig IOPQ 'I_ALU'
wordsig IJXX 'I_JMP'
wordsig ICALL 'I_CALL'
wordsig IRET 'I_RET'
wordsig IPUSHQ 'I_PUSHQ'
wordsig IPOPQ 'I_POPQ'
##### Symbolic represenations of Y86-64 function codes            #####
wordsig FNONE    'F_NONE'        # Default function code
##### Symbolic representation of Y86-64 Registers referenced      #####
wordsig RRSP     'REG_RSP'          # Stack Pointer
wordsig RNONE    'REG_NONE'         # Special value indicating "no register"
##### ALU Functions referenced explicitly ##########################
wordsig ALUADD 'A_ADD'       # ALU should add its arguments
##### Possible instruction status values                       #####
wordsig SBUB 'STAT_BUB' # Bubble in stage
wordsig SAOK 'STAT_AOK' # Normal execution
wordsig SADR 'STAT_ADR' # Invalid memory address
wordsig SINS 'STAT_INS' # Invalid instruction
wordsig SHLT 'STAT_HLT' # Halt instruction encountered
##### Signals that can be referenced by control logic ##############
##### Pipeline Register F ##########################################
wordsig F_predPC 'pc_curr->pc'      # Predicted value of PC
##### Intermediate Values in Fetch Stage ###########################
wordsig imem_icode  'imem_icode'      # icode field from instruction memory
wordsig imem_ifun   'imem_ifun'       # ifun  field from instruction memory
wordsig f_icode 'if_id_next->icode'  # (Possibly modified) instruction code
wordsig f_ifun 'if_id_next->ifun'   # Fetched instruction function
wordsig f_valC 'if_id_next->valc'   # Constant data of fetched instruction
wordsig f_valP 'if_id_next->valp'   # Address of following instruction
boolsig imem_error 'imem_error'      # Error signal from instruction memory
boolsig instr_valid 'instr_valid'    # Is fetched instruction valid?
##### Pipeline Register D ##########################################
wordsig D_icode 'if_id_curr->icode'   # Instruction code
wordsig D_rA 'if_id_curr->ra'      # rA field from instruction
wordsig D_rB 'if_id_curr->rb'      # rB field from instruction
wordsig D_valP 'if_id_curr->valp'     # Incremented PC
##### Intermediate Values in Decode Stage  #########################
wordsig d_srcA  'id_ex_next->srca'  # srcA from decoded instruction
wordsig d_srcB  'id_ex_next->srcb'  # srcB from decoded instruction
wordsig d_rvalA 'd_regvala'      # valA read from register file
wordsig d_rvalB 'd_regvalb'      # valB read from register file
##### Pipeline Register E ##########################################
wordsig E_icode 'id_ex_curr->icode'   # Instruction code
wordsig E_ifun  'id_ex_curr->ifun'    # Instruction function
wordsig E_valC  'id_ex_curr->valc'    # Constant data
wordsig E_srcA  'id_ex_curr->srca'    # Source A register ID
wordsig E_valA  'id_ex_curr->vala'    # Source A value
wordsig E_srcB  'id_ex_curr->srcb'    # Source B register ID
wordsig E_valB  'id_ex_curr->valb'    # Source B value
wordsig E_dstE 'id_ex_curr->deste'    # Destination E register ID
wordsig E_dstM 'id_ex_curr->destm'    # Destination M register ID
##### Intermediate Values in Execute Stage #########################
wordsig e_valE 'ex_mem_next->vale' # valE generated by ALU
boolsig e_Cnd 'ex_mem_next->takebranch' # Does condition hold?
wordsig e_dstE 'ex_mem_next->deste'      # dstE (possibly modified to be RNONE)
##### Pipeline Register M                  #########################
wordsig M_stat 'ex_mem_curr->status'     # Instruction status
wordsig M_icode 'ex_mem_curr->icode' # Instruction code
wordsig M_ifun  'ex_mem_curr->ifun' # Instruction function
wordsig M_valA  'ex_mem_curr->vala'      # Source A value
wordsig M_dstE 'ex_mem_curr->deste' # Destination E register ID
wordsig M_valE  'ex_mem_curr->vale'      # ALU E value
wordsig M_dstM 'ex_mem_curr->destm' # Destination M register ID
boolsig M_Cnd 'ex_mem_curr->takebranch' # Condition flag
boolsig dmem_error 'dmem_error'         # Error signal from instruction memory
##### Intermediate Values in Memory Stage ##########################
wordsig m_valM 'mem_wb_next->valm' # valM generated by memory
wordsig m_stat 'mem_wb_next->status' # stat (possibly modified to be SADR)
##### Pipeline Register W ##########################################
wordsig W_stat 'mem_wb_curr->status'     # Instruction status
wordsig W_icode 'mem_wb_curr->icode' # Instruction code
wordsig W_dstE 'mem_wb_curr->deste' # Destination E register ID
wordsig W_valE  'mem_wb_curr->vale'      # ALU E value
wordsig W_dstM 'mem_wb_curr->destm' # Destination M register ID
wordsig W_valM  'mem_wb_curr->valm' # Memory M value
####################################################################
#    Control Signal Definitions.                                   #
####################################################################
################ Fetch Stage     ###################################
## What address should instruction be fetched at
word f_pc = [
 # Mispredicted branch.  Fetch at incremented PC
 M_icode == IJXX && !M_Cnd : M_valA;
 # Completion of RET instruction
 W_icode == IRET : W_valM;
 # Default: Use predicted value of PC
 1 : F_predPC;
];
## Determine icode of fetched instruction
word f_icode = [
 imem_error : INOP;
 1: imem_icode;
];
# Determine ifun
word f_ifun = [
 imem_error : FNONE;
 1: imem_ifun;
];
# Is instruction valid?
bool instr_valid = f_icode in 
 {
    INOP, IHALT, IRRMOVQ, IIRMOVQ, IRMMOVQ, IMRMOVQ,
   IOPQ, IJXX, ICALL, IRET, IPUSHQ, IPOPQ };
# Determine status code for fetched instruction
word f_stat = [
 imem_error: SADR;
 !instr_valid : SINS;
 f_icode == IHALT : SHLT;
 1 : SAOK;
];
# Does fetched instruction require a regid byte?
bool need_regids =
 f_icode in {
    IRRMOVQ, IOPQ, IPUSHQ, IPOPQ, 
       IIRMOVQ, IRMMOVQ, IMRMOVQ };
# Does fetched instruction require a constant word?
bool need_valC =
 f_icode in {
    IIRMOVQ, IRMMOVQ, IMRMOVQ, IJXX, ICALL };
# Predict next value of PC
word f_predPC = [
 f_icode in {
    IJXX, ICALL } : f_valC;
 1 : f_valP;
];
################ Decode Stage ######################################
## What register should be used as the A source?
word d_srcA = [
 D_icode in {
    IRRMOVQ, IRMMOVQ, IOPQ, IPUSHQ  } : D_rA;
 D_icode in {
    IPOPQ, IRET } : RRSP;
 1 : RNONE; # Don't need register
];
## What register should be used as the B source?
word d_srcB = [
 D_icode in {
    IOPQ, IRMMOVQ, IMRMOVQ  } : D_rB;
 D_icode in {
    IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;
 1 : RNONE;  # Don't need register
];
## What register should be used as the E destination?
word d_dstE = [
 D_icode in {
    IRRMOVQ, IIRMOVQ, IOPQ} : D_rB;
 D_icode in {
    IPUSHQ, IPOPQ, ICALL, IRET } : RRSP;
 1 : RNONE;  # Don't write any register
];
## What register should be used as the M destination?
word d_dstM = [
 D_icode in {
    IMRMOVQ, IPOPQ } : D_rA;
 1 : RNONE;  # Don't write any register
];
## What should be the A value?
##  DO NOT MODIFY THE FOLLOWING CODE.
## No forwarding.  valA is either valP or value from register file
word d_valA = [
 D_icode in {
    ICALL, IJXX } : D_valP; # Use incremented PC
 1 : d_rvalA;  # Use value read from register file
];
## No forwarding.  valB is value from register file
word d_valB = d_rvalB;
################ Execute Stage #####################################
## Select input A to ALU
word aluA = [
 E_icode in {
    IRRMOVQ, IOPQ