前面一段时间fpga课整了个比较神奇的搭配?就交通信号灯(有上FPGA课的人应该知道这是一个比较基础的内容)配合VGA显示,弄了点东西忍不住分享一下。
总体上我这篇文章就重点讲解一下VGA显示模块和逻辑控制模块,像led和数码管模块我就不说了(也没啥东西可以说)
我先放个结果在这
话不多说先贴一段代码
module control_place(
input clk_1s,
input rst,
input control_auto,
input contrl_re,
output reg [5:0]time_data_10,
output reg [5:0]time_data_0,
output reg [1:0]light_in_NS,
output reg [1:0]light_in_WE,
output reg ss_time
);
initial
begin
// 00是绿灯,01是黄灯 ,10是红灯
light_in_NS = 2'b01;
light_in_WE = 2'b01;
time_data_10 = 0;
time_data_0 = 5;
ss_time = 0;
end
//设定逻辑
always@(posedge clk_1s or negedge rst)
begin
if (!rst) begin
light_in_NS = 2'b01;
light_in_WE <= 2'b01;
time_data_10 <= 0;
time_data_0 <= 5;
ss_time <= 0;
end
else begin
if((time_data_0 == 1|| time_data_0 == 0)&& time_data_10 == 0)
if(control_auto)
begin
if(light_in_NS == 'b00)
begin
light_in_NS <= 'b01;
light_in_WE <= 'b10;
time_data_10 <= 0;
time_data_0 = 5;
end
else if(light_in_NS == 'b01)
begin
light_in_NS <= 'b10;
light_in_WE <= 'b00;
time_data_10 <= 2;
time_data_0 <= 5;
ss_time = 0;
end
else if(light_in_WE == 'b00)
begin
light_in_NS <= 'b10;
light_in_WE <= 'b01;
time_data_10 <= 0;
time_data_0 = 5;
end
else if(light_in_WE == 'b01)
begin
light_in_NS <= 'b00;
light_in_WE <= 'b10;
time_data_10 <= 2;
time_data_0 <= 5;
ss_time = 0;
end
end
else
begin
if(contrl_re)
begin
if(light_in_NS == 'b00 || light_in_WE == 'b01)
begin
light_in_NS <= 'b00;
light_in_WE <= 'b10;
end
else
begin
light_in_NS <= 'b10;
light_in_WE <= 'b01;
time_data_0 = 5;
time_data_10 = 0;
end
end
else
begin
if(light_in_WE == 'b00 || light_in_NS == 'b01)
begin
light_in_WE <= 'b00;
light_in_NS <= 'b10;
end
else
begin
light_in_WE <= 'b10;
light_in_NS <= 'b01;
time_data_0 = 5;
time_data_10 = 0;
end
end
end
else
if(!control_auto)
begin
time_data_10 = 0;
if(time_data_0 >= 5)
time_data_0 = 5;
end
if(time_data_0 == 0)
begin
if(time_data_10 != 0)
time_data_10 = time_data_10 - 1;
time_data_0 = 9;
end
else if(time_data_0 == 5