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FPGA调用OLED
FPGA调用OLED因为参加硬禾学堂的寒假在家一起练的活动,所以记录一些中间遇到的困难和解决方法,当然我因为刚刚接触FPGA,所以在了解了一定的驱动芯片的指令之后,发现电子森林中有驱动TFT_LCD的程序,所以直接拿过来修改了OLED介绍样式介绍OLED屏幕的特点为:0.91寸七针,SPI协议通信;其中我的板子上面的七针有CLK(有些地方是用D0代替),MOSI(也可以用D1)个人经验我建议大家如果说是刚刚入手OLED,直接先把通信协议调好,然后把OLED初始化的程序发送给OLED再原创 2021-03-11 11:09:14 · 2098 阅读 · 1 评论 -
26 Module addsub
An adder-subtractor can be built from an adder by optionally negating one of the inputs, which is equivalent to inverting the input then adding 1. The net result is a circuit that can do two operations: (a + b + 0) and (a + ~b + 1). SeeWikipediaif you w...原创 2021-03-06 18:12:06 · 681 阅读 · 0 评论 -
25 Module cseladd
One drawback of the ripple carry adder (Seeprevious exercise) is that the delay for an adder to compute the carry out (from the carry-in, in the worst case) is fairly slow, and the second-stage adder cannot begin computingitscarry-out until the first-s...原创 2021-03-05 11:06:30 · 539 阅读 · 1 评论 -
24 Module fadd
In this exercise, you will create a circuit with two levels of hierarchy. Yourtop_modulewill instantiate two copies ofadd16(provided), each of which will instantiate 16 copies ofadd1(which you must write). Thus, you must writetwomodules:top_modul...原创 2021-02-25 14:20:45 · 1319 阅读 · 0 评论 -
Module add
不好意思写,每日一题,太打脸了,看着写吧,题目如上具体要求:You are given a moduleadd16that performs a 16-bit addition. Instantiate two of them to create a 32-bit adder. One add16 module computes the lower 16 bits of the addition result, while the second add16 module computes th..原创 2021-02-24 21:59:39 · 554 阅读 · 0 评论 -
每日一题-Module shift8
This exercise is an extension of module_shift. Instead of module ports being only single pins, we now have modules with vectors as ports, to which you will attach wire vectors instead of plain wires. Like everywhere else in Verilog, the vector length of t.原创 2021-02-22 16:44:31 · 1251 阅读 · 1 评论 -
2021-01-11
//14_Vector3module top_module ( input [4:0] a, b, c, d, e, f, output [7:0] w, x, y, z );// // assign { ... } = { ... }; assign {w,x,y,z} = {a,b,c,d,e,f,1'b1,1'b1};endmodule//15_Vectorrmodule top_module( input [7:0] in, out.原创 2021-01-11 20:17:56 · 154 阅读 · 0 评论