One drawback of the ripple carry adder (See previous exercise) is that the delay for an adder to compute the carry out (from the carry-in, in the worst case) is fairly slow, and the second-stage adder cannot begin computing its carry-out until the first-stage adder has finished. This makes the adder slow. One improvement is a carry-select adder, shown below. The first-stage adder is the same as before, but we duplicate the second-stage adder, one assuming carry-in=0 and one assuming carry-in=1, then using a fast 2-to-1 multiplexer to select which result happened to be correct.
In this exercise, you are provided with the same module
add16
as the previous exercise, which adds two 16-bit numbers with carry-in and produces a carry-out and 16-bit sum. You must instantiate three of these to build the carry-select adder, using your own 16-bit 2-to-1 multiplexer.Connect the modules together as shown in the diagram below. The provided module
add16
has the following declaration:
module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );
上面的英文大致意思是,之前的加法器有很大的缺陷,1 是计算逐位相加时的进位的延迟是相当缓慢的,2 是在第一个加法器没有计算完成的时候之前,第二个加法器都是不能开始工作的。由于以上2点原因使得上一个32位加法器(24 Module fadd)相当慢。
所以今天就改进一下这个加法器,其中改进后的方案是可选择进位加法器,展示在图1,图1中的第一个加法器之前的结构是一样的,但是我们复制两个16位加法器,一个假设进位为0,另一个假设进位为1,接着使用一个快速的2选1复用器去选择哪一个结果才是正确的
在这个练习中,你们被提供和第24题一样的16位加法器,这个16位加法器可以加两个16位数并且带上输入的进位,之后它会产生一个输出和16位的和
所以我们应该先实例化三个16位加法器,之后用case语句进行选择,在这个case语句中把低16位的进位输出当做激励信号,程序如下:
module top_module(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire SW;
reg [15:0] sum1;
reg [15:0] sum2;
add16 add16_1( //低16位,cin为0
.a(a[15:0]),
.b(b[15:0]),
.sum(sum[15:0]),
.cout(SW)
);
always@(SW) begin
case(SW)
1'b0:begin
sum[31:16] = sum1[15:0];
end
1'b1:begin
sum[31:16] = sum2[15:0];
end
endcase
end
add16 add16_2( //高16位,cin为0
.a(a[31:16]),
.b(b[31:16]),
.sum(sum1[15:0])
);
add16 add16_3( //高16位,cin为1
.a(a[31:16]),
.b(b[31:16]),
.cin(1),
.sum(sum2[15:0])
);
endmodule