【条款10】Have assignment operators return a reference to *this

运算符重载的一个原则就是:与内置类型的运算符具有一致的性质。

对于赋值操作符,内置类型可以连锁赋值,即

x=y=z=1;

为了实现“连锁赋值”,赋值操作符必须返回一个reference指向操作符的左侧实参。

class A{
public:
	A& operator=(const A& a)
	{
		...
		return *this;
	}
	
	A& operator+=(const A& a)
	{
		...
		return *this;
	}
};

即所有与赋值相关的运算都得这样做。

注意:由于要返回*this,所以赋值运算符只能重载为类的成员,而不能重载为友元!!!





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In Verilog, a non-net refers to a variable that is not a wire or a register, but rather a constant or a parameter. Concurrent assignment refers to the assignment of a value to a variable using the "=" operator in a module outside of any procedural blocks (such as always or initial blocks). A concurrent assignment to a non-net is not allowed in Verilog. This is because a non-net does not have a storage element and cannot hold a value assigned to it. Instead, it is typically used as a constant or a parameter that is available for use in the module. To assign a value to a non-net, it should be done within a procedural block using the appropriate assignment operator (such as "<=" for registers or "assign" for wires). Alternatively, the value can be passed as an argument to the module using the parameter keyword. For example: module my_module #(parameter WIDTH = 8) ( input clk, input [WIDTH-1:0] data_in, output [WIDTH-1:0] data_out ); // This is a non-net parameter parameter ADD_VALUE = 5; // This is a register that can be assigned using the "=" operator within an always block reg [WIDTH-1:0] register_data; always @(posedge clk) begin register_data <= data_in + ADD_VALUE; end // This is a wire that can be assigned using the "assign" keyword assign data_out = register_data; endmodule In this example, ADD_VALUE is a non-net parameter that is used in the always block to add a constant value to the input data. The register_data variable is assigned using the "=" operator within the always block. The data_out wire is assigned using the "assign" keyword.

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