初始化序列(Init sequence)按下面的填,也是从H-Jtag的script扒出来的,我简单做了下注释。
##-------Action-----Value0------Value1
Setmem 32-Bit 0x53000000 0x00000000 ; pWTCON , 看门狗定时器控制寄存器
Setmem 32-Bit 0x4A000008 0xFFFFFFFF ; INTMSK , 中断屏蔽寄存器
Setmem 32-Bit 0x4A00001C 0x000007FF ; INTSUBMSK , 针对INTMAK具体化的一个中断请求屏蔽寄存器
Setmem 32-Bit 0x53000000 0x00000000 ; pWTCON , 看门狗定时器控制寄存器
Setmem 32-Bit 0x56000050 0x000055AA ; rGPFCON , Port F control
Setmem 32-Bit 0x4C000014 0x00000007 ; CLKDIVN , CPU时钟分频控制寄存器
Setmem 32-Bit 0x4C000000 0x00FFFFFF ; LOCKTIME , 锁时计数寄存器
Setmem 32-Bit 0x4C000004 0x00061012 ; MPLLCON , MPLL寄存器
Setmem 32-Bit 0x4C000008 0x00040042 ; UPLLCON , UPLL寄存器
Setmem 32-Bit 0x48000000 0x22111120 ; Bus width & wait status
Setmem 32-Bit 0x48000004 0x00002F50 ; Boot ROM control
Setmem 32-Bit 0x48000008 0x00000700 ; BANK1 control
Setmem 32-Bit 0x4800000C 0x00000700 ; BANK2 control
Setmem 32-Bit 0x48000010 0x00000700 ; BANK3 control
Setmem 32-Bit 0x48000014 0x00000700 ; BANK4 control
Setmem 32-Bit 0x48000018 0x0007FFFC ; BANK5 control
Setmem 32-Bit 0x4800001C 0x00018005 ; BANK6 control
Setmem 32-Bit 0x48000020 0x00018005 ; BANK7 control
Setmem 32-Bit 0x48000024 0x008E0459 ; DRAM/SDRAM refresh
Setmem 32-Bit 0x48000028 0x00000032 ; Flexible Bank Size
Setmem 32-Bit 0x4800002C 0x00000030 ; Mode register set for SDRAM
Setmem 32-Bit 0x48000030 0x00000030 ; Mode register set for SDRAM
##-------Action-----Value0------Value1
Setmem 32-Bit 0x53000000 0x00000000 ; pWTCON , 看门狗定时器控制寄存器
Setmem 32-Bit 0x4A000008 0xFFFFFFFF ; INTMSK , 中断屏蔽寄存器
Setmem 32-Bit 0x4A00001C 0x000007FF ; INTSUBMSK , 针对INTMAK具体化的一个中断请求屏蔽寄存器
Setmem 32-Bit 0x53000000 0x00000000 ; pWTCON , 看门狗定时器控制寄存器
Setmem 32-Bit 0x56000050 0x000055AA ; rGPFCON , Port F control
Setmem 32-Bit 0x4C000014 0x00000007 ; CLKDIVN , CPU时钟分频控制寄存器
Setmem 32-Bit 0x4C000000 0x00FFFFFF ; LOCKTIME , 锁时计数寄存器
Setmem 32-Bit 0x4C000004 0x00061012 ; MPLLCON , MPLL寄存器
Setmem 32-Bit 0x4C000008 0x00040042 ; UPLLCON , UPLL寄存器
Setmem 32-Bit 0x48000000 0x22111120 ; Bus width & wait status
Setmem 32-Bit 0x48000004 0x00002F50 ; Boot ROM control
Setmem 32-Bit 0x48000008 0x00000700 ; BANK1 control
Setmem 32-Bit 0x4800000C 0x00000700 ; BANK2 control
Setmem 32-Bit 0x48000010 0x00000700 ; BANK3 control
Setmem 32-Bit 0x48000014 0x00000700 ; BANK4 control
Setmem 32-Bit 0x48000018 0x0007FFFC ; BANK5 control
Setmem 32-Bit 0x4800001C 0x00018005 ; BANK6 control
Setmem 32-Bit 0x48000020 0x00018005 ; BANK7 control
Setmem 32-Bit 0x48000024 0x008E0459 ; DRAM/SDRAM refresh
Setmem 32-Bit 0x48000028 0x00000032 ; Flexible Bank Size
Setmem 32-Bit 0x4800002C 0x00000030 ; Mode register set for SDRAM
Setmem 32-Bit 0x48000030 0x00000030 ; Mode register set for SDRAM