1、获取上升沿下降沿
always @(posedge CLK_50M or negedge rst_n)
begin
if(!rst_n)
begin
{spi_cs_2,spi_cs_1} <= 2'b11;
{spi_sck_2,spi_sck_1} <= 2'b00;
{spi_mosi_2,spi_mosi_1} <= 2'b00;
end
else
begin
{spi_cs_2,spi_cs_1} <= {spi_cs_1,nCE};
{spi_sck_2,spi_sck_1} <= {spi_sck_1,CLK_SPI};
{spi_mosi_2,spi_mosi_1} <= {spi_mosi_1,DATAIN};
end
end
assign spi_cs_pos = ~spi_cs_2 &spi_cs_1;
assign spi_cs_flag = spi_cs_2;
assign spi_sck_neg = ~spi_sck_1&spi_sck_2; //negedge
assign spi_sck_pos = ~spi_sck_2&spi_sck_1; //posedge
assign spi_mosi_flag = spi_mosi_2;
assign spi_over = spi_cs_pos;
2、语句理解
assign dataout = data_sel ? dataout_reg : rxdata ;
解释:data_sel是1 的时候为assign dataout =dataout_reg;
data_sel是0 的时候为assign dataout =rxdata;
3、错误代码为*is not a constant
实例代码如下:
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如果这样写编译时会报错:
Error: Error (10734): Verilog HDL error at seg7_controller.v(82): avs_s1_address is not a constant
File: f:/fpga/niosii_mpc/de3_seg/ip/seg7_controller/seg7_controller.v Line: 82
错误提示解释说avs_s1_address不是常值。代码可以修改为:
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