Verilog HDL 学习笔记1-data type

2013-05-02 18:13:20

　　开始做毕设将近有两个月了，主要做的是《基于FPGA的基带解调器的设计》，其中最核心的部分是4096点FFT的设计。截止到目前，算是完成了4096点FFT的模块设计（仅仅modelsim仿真通过）。通过两个月的学习，对Verilog HDL有了新的认识。学习贵在总结，遂将心得体会记录！

Verilog HDL 学习笔记1-data type

　　接触HDL时间其实挺长了，最开始接触的是VHDL，写过的最复杂的设计是一个自动量程的频率计。大三的ASIC课上接触到了Verilog HDL，从图书馆借了本书（书名具体叫啥忘了）准备好好学。看了该书一段时间（也就几天）后，发现Verilog 语法竟然这么复杂......直接扼杀了我对Verilog HDL的三分钟热度。后来才发现，我借的那本书是将verilog 1995标准直接翻译过来的，可综合语法和用来设计testbench等（水平有限，不太清楚不可综合的语法具体用来干啥）混在了一起。其实当时我想用到的只是可综合的部分，要是当时看的书能清楚地指明这点，估计也不会走这么多弯路了。可见，对于入门者而言，选对书很重要！后来在学长的推荐下，看了夏宇闻老师的《Verilog 数字系统设计教程》，感觉挺不错的！以下的学习笔记很大部分出自该书。

　　絮絮叨叨这么多，现在要开始进入正题了！无论学习任何语言，第一步毫无疑问是学习语法。而学习verilog语法，第一个疑惑点就在于 Verilog HDL的data type。对于可综合的设计而言，疑惑就在于 wire 和 reg 的区别。

　　闲话不多说，先上Verilog 2001（IEEE Standard Verilog Hardware Description Language）对于data type 的描述：

There are two main groups of data types: the variable data types and the net data types. These two groups differ in the way that they are assigned and hold values. They also represent different hardware structures.

　　Net declarations：The net data types shall represent physical connections between structural entities, such as gates. A net shall not store a value (except for the trireg net). Instead, its value shall be determined by the values of its drivers, such as a continuous assignment or a gate. See Section 6 and 7. for definitions of these constructs. If no driver is connected to a net, its value shall be high-impedance (z) unless the net is a trireg, in which case it shall hold the previously driven value. It is illegal to redeclare a name already declared by a net, parameter,or variable declaration (see 3.12).

　　Variable declarations：A variable is an abstraction of a data storage element. A variable shall store a value from one assignment to the next. An assignment statement in a procedure acts as a trigger that changes the value in the data storage element. The initialization value for reg, time, and integer data types shall be the unknown value, x. The default initialization value for real and realtime variable datatypes shall be 0.0. If a variable declaration assignment is used (see 6.2.1), the variable shall take this value as if the a