module top_module(
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q);
always@(posedge clk, posedge areset) begin
if(areset)
q = 4'b0;
else begin
if(ena)
q = {1'b0, q[3:1]};
if(load)
q = data;
end
end
endmodule
hdlbits.01xz.net /Circuits/Sequential Logic/Shift Registers/4-bit shift register
最新推荐文章于 2024-06-07 23:09:19 发布