module top_module (
input clk,
input a,
output q );
always @(posedge clk) begin
if(a)
q = 0;
else
q = 1;
end
endmodule
hdlbits.01xz.net /Verification:Reading Simulations/Build a circuit from a simulation waveform/S.7.
最新推荐文章于 2024-05-31 22:50:46 发布