Allegro DRC错误代码汇总

Allegro DRC错误代码

 

    DRC 错误代码

代码

相关对象

说明

单一字符代码

L

Line

走线

P

Pin

元件脚

V

Via

贯穿孔

K

Keep in/out

允许区域/禁止区域

C

Component

元件层级

E

Electrical Constraint

电气约束

J

T-Junction

呈现T形的走线

I

Island Form

PinVia围成的负片孤铜

 

 

 

错误代码前置码说明

 

 

W

Wire

与走线相关的错误

D

Design

与整个电路板相关的错误

M

Soldemask

与防焊层相关的错误

 

 

 

错误代码后置码说明

 

 

S

Shape/Stub

与走线层的Shape或分支相关的错误

N

Not  Allowed

与不允许的设置相关的错误

W

Width

与宽度相关的错误

 

 

 

双字符错误代码

 

 

BB

Bondpad to Bondpad

Bondpad之间的错误

BL

Bondpad to Line

BondpadLine之间的错误

BS

Bondpad to Shape

BondpadShape 之间的错误

CC

Package to Package

Package之间的 Spacing 错误

Symbol Soldermask to Symbol

Soldermask零件防焊层之间的Spacing 错误

DF

Differential Pair Length Tolerance

差分对走线的长度误差过长

Differential Pair Primary Max Separation

差分对走线的主要距离太大

Differential Pair Secondary Max Separation

差分对走线的次要距离太大

Differential Pair Secondary Max Length

差分对走线的次要距离长度过长

DI

Design Constraint Negative Plane Island

负片孤铜的错误

ED

Propagation-Delay

走线的长度错误

Relative-Propagation-Delay

走线的等长错误

EL

Max Exposed Length

走线在外层(TOP&BOTTOM)的长度过长

EP

Max Net Parallelism Length-Distance Pair

已超过Net之间的平行长度

ES

Max Stub Length

走线的分支过长

ET

Electrical Topology

走线连接方式的错误

EV

Max Via Count

已超过走线使用的VIA的最大数目

EX

Max Crosstalk

已超过Crosstalk

Max Peak Crosstalk

已超过Peak Crosstalk

HH

Hold to Hold Spacing

钻孔之间的距离太近

HW

Diagonal Wire to Hold Spacing

斜线与钻孔之间的距离太近

Hold to Orthogonal Wire Spacing

钻孔与垂直/水平线之间的距离太近

IM

Impedance Constraint

走线的阻抗值错误

JN

T Junction Not Allowed

走线呈T形的错误

KB

Route Keepin  to Bondpad

BondpadKeepin之外

Route keepout  to Bondpad

Bondpadkeepout之内

Via Keepout  to  Bondpad

BondpadVia Keepout之内

KC

Package to Place Keepin Spacing

元件在Place Keepin之外

Package to Place Keepout Spacing

元件在Place Keepout之内

KL

Line to Route Keepin Spacing

走线在Route Keepin之外

Line to Route Keepout Spacing

走线在Route Keepout之内

KS

Shape to Route Keepin Spacing

ShapeRoute Keepin之外

Shape to Route Keepout Spacing

ShapeRoute Keepout之内

KV

BBVia to Route Keepin Spacing

BBViaRoute Keepin之外

BBVia to Route Keepout Spacing

BBViaRoute Keepout之内

BBVia to Via Keepout Spacing

BBViaVia Keepout之内

Test Via to Route Keepin Spacing

Test ViaRoute Keepin之外

Test Via to Route Keepout Spacing

Test ViaRoute Keepout之内

Test Via to Via Keepout Spacing

Test ViaVia Keepout之内

Through Via to Route Keepin Spacing

Through ViaRoute Keepin之外

Through Via to Route Keepout Spacing

Through ViaRoute Keepout之内

Through Via to Via Keepout Spacing

Through ViaVia Keepout之内

LB

Min Self Crossing Loopback Length

LL

Line to Line Spacing

走线之间太近

LS

Line to Shape Spacing

走线与Shape 太近

LW

Min Line Width

走线的宽度太细

Min Neck Width

走线变细的宽度太细

MA

 Soldermask Alignment Error Pad

Soldermask Tolerance太小

MC

Pin/Via Soldermask to Symbol Soldermask

PadSymbol Soldermask之间的错误

MM

Pin/Via Soldermask to Pin/Via Soldermask

Pad  Soldermask之间的错误

PB

Pin to Bondpad

PinBondpad之间的错误

PL

Line to SMD Pin Spacing

走线与SMD元件脚太近

Line to Test Pin Spacing

走线与Test元件脚太近

Line to Through Pin Spacing

走线与Through元件脚太近

PP

SMD Pin to SMD Pin Spacing

SMD元件脚与SMD元件脚太近

SMD Pin to Test Pin Spacing

SMD元件脚与Test元件脚太近

Test Pin to Test Pin Spacing

Test元件脚与Test元件脚太近

Test Pin to Through Pin Spacing

Test元件脚与Through元件脚太近

Through Pin to SMD Pin Spacing

Through元件脚与SMD元件脚太近

Through Pin to Through Pin Spacing

Through元件脚与Through元件脚太近

PS

Shape to SMD Pin Spacing

ShapeSMD元件脚太近

Shape to Test Pin Spacing

ShapeTest元件脚太近

Through Pin to Shape Spacing

Through元件脚与Shape太近

PV

BBVia to SMD Pin Spacing

BBViaSMD元件脚太近

BBVia to Test Pin Spacing

BBViaTest元件脚太近

BBVia to Through Pin Spacing

BBVia Through元件脚太近

SMD Pin to Test Via Spacing

SMD PinTest Via太近

SMD Pin to Through Via Spacing

SMD PinThrough Via太近

Test Pin to Test Via Spacing

Test PinTest Via太近

Test Pin to Through Via Spacing

Test PinThrough Via太近

Test Via to Through Pin Spacing

Test ViaThrough Pin太近

Through Pin to Through Via Spacing

Through PinThrough Via太近

RC

Package to Hard Room

元件在其他的Room之内

RE

Min Length Route End Segment at 135Degree

Min Length Route End Segment at 45/90Degree

 SB

135Degree Turn to Adjacent Crossing Distance

90Degree Turn to Adjacent Crossing Distance

SL

Min Length Wire Segment

Min Length Single Segment Wire

SN

Allow on Etch Subclass

允许在走线层上

SO

Segment Orientaion

BB

Bondpad to Bondpad

Bondpad之间的错误

SS

Shape to Shape

Shape之间的错误

TA

Max Turn Angle

VB

Via to Bondpad

Via Bondpad之间的错误

VG

Max BB Via Stagger Distance

同一段线的BB Via之间的距离太长

Min BB Via Gap

BB Via之间太近

Min BB Via Stagger Distance

同一段线的BB Via之间的距离太近

Pad/Pad Direct Connect

Pad 在另一个Pad 之上

VL

BB Via to Line Spacing

BB Via与走线太近

Line to Through Via Spacing

走线与Through Via太近

Line to Test Via Spacing

走线与Test Via太近

VS

BB Via to Shape Spacing

BB ViaShape太近

Shape to Test Via Spacing

Shape Test Via太近

Shape to Through Via Spacing

ShapeThrough Via太近

VV

BB Via to BB Via  Spacing

BB Via之间太近

BB Via to Test Via Spacing

BB ViaTest Via太近

BB Via to Through Via Spacing

BB ViaThrough Via太近

Test Via to Test Via Spacing

Test Via之间太近

Test Via to Through Via Spacing

Test ViaThrough Via太近

Through Via to Through Via Spacing

Through Via之间太近

WA

Min Bonding Wire Length

Bonding Wire 长度太短

WE

Min End Segment Length

Min Length Wire End Segment at 135Degree

Min Length Wire End Segment at 45/90Degree

WI

Max Bonding Wire Length

Bonding Wire 长度太长

WW

Diagonal Wire to Diagonal Wire Spacing

斜线之间太近

Diagonal Wire to Orthogonal Wire Spacing

斜线与垂直/水平线之间的距离太近

Orthogonal Wire to Orthogonal Wire Spacing

垂直/水平线之间的距离太近

WX

Max Number of Crossing

Min Distance between Crossing

XB

135 Degree Turn to Adjacent Crossing Distance

90 Degree Turn to Adjacent Crossing Distance

XD

Externally Determined Violation

XS

Crossing to Adjacent Segment Distances

 

 

 

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Allegro DRC是PCB设计软件Allegro的一个功能,用于检测和解决设计的电气规则冲突。DRC错误通常是指在PCB设计过程发现的违反电气规则的问题。 DRC错误可能出现的原因有很多,如器件布局不当、信号线过于接近、导线之间有短路等。这些错误可能导致电路功能异常、噪音干扰等问题。 当Allegro检测到潜在的DRC错误时,会在设计环境进行提示和标记。设计人员可以通过查看错误报告来了解具体的错误类型和位置。常见的DRC错误包括:阻抗匹配错误、分层错误、间距太小、信号完整性等。 为了解决DRC错误,设计人员可以采取以下措施: 1. 仔细检查器件布局,确保元件之间的间距足够大,避免短路和干扰。 2. 检查信号线的路径,确保它们之间的距离足够,并避免距离过近引起的互相干扰。 3. 优化分层布局,避免不恰当的分层设置导致信号完整性问题。 4. 配置正确的阻抗匹配规则,确保信号的正常传输。 5. 使用Allegro提供的工具和功能,如自动布线和电气规则检查等,辅助解决DRC错误。 以防止DRC错误的出现,设计人员还可以通过充分了解电气规则、合理规划布局、应用良好的信号完整性原则等来提高设计质量。 总之,Allegro DRC错误是PCB设计过程常见的问题,设计人员可以通过仔细检查、优化布局和配置正确的规则来解决这些错误,以确保设计的准确性和稳定性。

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