STM32——串口溢出ORE的前世今生

当数据接收区或者FIFO区有数据或者满时，又有新数据进来，会导致发生溢出错误，一旦发生溢出错误，RX 移位寄存区虽然能有新数据不断的覆盖，但是数据不会到达RXR或FIFO（现象是：RXNE在ORE置位时不会被置位），导致程序中不能读到新的数据。只有通过ICR清除ORE才能使得RXNE在接收到新数据时置位。

串口框图

溢出错误属于串口接收

USART receiver

溢出错误发生的原因

1. FIFO mode disabled
   An overrun error occurs if a character is received and RXNE has not been reset.
   Data can not be transferred from the shift register to the RDR register until the RXNE
   bit is cleared. The RXNE flag is set after every byte reception.
   An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced.
2. FIFO mode enabled
   An overrun error occurs when the shift register is ready to be transferred and the receive FIFO is full.
   Data can not be transferred from the shift register to the USART_RDR register until there is one free location in the RXFIFO. The RXFNE flag is set when the RXFIFO is not empty.
   An overrun error occurs if the RXFIFO is full and the shift register is ready to be transferred.

溢出错误后果

– the ORE bit is set;
– the RDR content will not be lost. The previous data is available by reading the USART_RDR register.
– The first entry in the RXFIFO will not be lost. It is available by reading the USART_RDR register.
– the shift register will be overwritten. After that, any data received during overrun is lost.
– An interrupt is generated if either the RXFNEIE or EIE bit is set.

清除溢出错误

The ORE bit is reset by setting the ORECF bit in the USART_ICR register.
Note: The ORE bit, when set, indicates that at least 1 data has been lost.

When the FIFO mode is disabled, there are two possibilities
• if RXNE=’1’, then the last valid data is stored in the receive register (RDR) and can be read,
• if RXNE=’0’, the last valid data has already been read and there is nothing left to be read in the RDR register. This case can occur when the last valid data is read in the RDR register at the same time as the new (and lost) data is received.

寄存器 ISR Bit 3 ORE: Overrun error

This bit is set by hardware when the data currently being received in the shift register is ready to be transferred into the USART_RDR register while RXNE=’1’ (RXFF = ’1’ in case FIFO mode is enabled).

It is cleared by a software, writing ’1’ to the ORECF, in the USART_ICR register.

An interrupt is generated if RXNEIE/ RXFNEIE=’1’ or EIE = ’1’ in the USART_CR1 register.
0: No overrun error
1: Overrun error is detected

Note:

1. When this bit is set, the USART_RDR register content is not lost but the shift register is overwritten.
2. An interrupt is generated if the ORE flag is set during multi buffer communication if the EIEbit is set.
3. This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in the USART_CR3 register