zynq spi

Master Mode

In master mode, the SPI I/O interface can transmit data to a slave or initiate a transfer to receive data
from a slave. The controller selects one slave device at the time using one of the three slave select
lines. If more than three slave devices need to be connected to the master, it is possible to add an
external peripheral select 3-to-8 decode on the board
 

Data Transfer

The SCLK clock and MOSI signals are under control of the master. Data to be transmitted is written
into the TxFIFO by software using register writes and then unloaded for transmission by the
controller hardware in a manual or automatic start sequence. Data is driven onto the master output
(MOSI) data pin. Transmission is continuous while there is data in the TxFIFO.
Data is received serially on the MISO data pin and is loaded 8 bits at a time into the RxFIFO. Software
reads the RxFIFO using register reads. For every “n” bytes written to the TxFIFO, there will be “n”
bytes stored in RxFIFO that must be read by software before starting the next transfer
 

 Auto/Manual SS and Start
 

FIFO Interrupts

Interrupt Register Bits, Logic Flow

 

Start-up Sequence

问题

int SPIChipSelectInit(SPI_CS_ID_T ChipSelect)
{
	unsigned int GPIOBankID, GPIOPinID;

	if(JUDGE_SPI_CS_IS_MIO(ChipSelect))
	{
		return 0;
	}

	GPIOBankID = GET_SPI_CS_GPIO_BANK_ID(ChipSelect);
	GPIOPinID = GET_SPI_CS_GPIO_PIN_ID(ChipSelect);

	// set GPIO direction is output
	GPIOSetPinDirection(GPIOBankID, GPIOPinID, GPIO_DIR_OUT);

	// enable output
	GPIOPinOutEnable(GPIOBankID, GPIOPinID);

	// set initialization value
	GPIOWritePinData(GPIOBankID, GPIOPinID, GPIO_OUTPUT_HIGH);

	return 0;
}