中值滤波去除噪点项目设计书

最新推荐文章于 2022-01-11 07:40:00 发布

u013024206

最新推荐文章于 2022-01-11 07:40:00 发布

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分类专栏： fpga 文章标签： fpga图像算法中值滤波

本文链接：https://blog.csdn.net/u013024206/article/details/47378483

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这是毕业第一年的时候写的一个项目程序，贡献出来，供大家学习，交流，不做商用。

这是fpga做的图像中值滤波，图像的分辨率是256*256。以下是详细东西，有这个算法的详细思考过程，和程序，还有做出来的效果。效果是根据fpga算法用matlab仿真出来的。

以下是项目涉及的程序：

/*
	求最小值中的最大值。
*/
`timescale 1ns/1ps

module max_of_3(
	//input
	vclk,
	vsync,
	hsync,
	vden,
	min_x1,
	min_x2,
	min_x3,
	//output
	vsync_out,
	hsync_out,
	vden_out,
	max_of_min
);
input vclk;
input vsync,hsync,vden;
input [23:0] min_x1,min_x2,min_x3;
output [23:0] max_of_min;
output vsync_out,hsync_out,vden_out;
reg [23:0] max_of_min=24'h0;
reg vsync_reg,hsync_reg,vden_reg;

always@(posedge vclk)
begin
	if(min_x1>min_x2)
		begin
			if(min_x3>min_x1)
				begin
					max_of_min<=min_x3;
				end
			else
				begin
					max_of_min<=min_x1;
				end
		end	
		else
			begin
				if(min_x3>min_x2)
					begin
						max_of_min<=min_x3;
					end
				else 
					begin
						max_of_min<=min_x2;
					end
			end
end
/****Delay Signals************************/
always @ (posedge vclk)
begin
	vsync_reg <= vsync;
	hsync_reg <= hsync;
	vden_reg  <= vden;
end

assign vsync_out = vsync_reg;
assign hsync_out = hsync_reg;
assign vden_out  = vden_reg;
/****Delay Signals************************/
endmodule

/*	
	求中值的中值。
*/
`timescale 1ns/1ps

module mid_of_3(
	//input
	vclk,
	vsync,
	hsync,
	vden,
	mid_x1,
	mid_x2,
	mid_x3,
	//output
	vsync_out,
	hsync_out,
	vden_out,
	mid_of_mid
);
input vclk;
input vsync,hsync,vden;
input [23:0] mid_x1,mid_x2,mid_x3;
output [23:0] mid_of_mid;
output vsync_out,hsync_out,vden_out;

reg [23:0] mid_of_mid=24'h0;
reg vsync_reg,hsync_reg,vden_reg;

always@(posedge vclk)
begin
	if(mid_x1<mid_x2)
		begin
			if(mid_x3<mid_x1)
				begin
					mid_of_mid<=mid_x1;
				end
			else if(mid_x3<mid_x2)
				begin
					mid_of_mid<=mid_x3;
				end
			else
				begin
					mid_of_mid<=mid_x2;
				end
		end	
		else
			begin
				if(mid_x3<mid_x2)
					begin
						mid_of_mid<=mid_x2;
					end
				else if(mid_x3<mid_x1)
					begin
						mid_of_mid<=mid_x3;
					end
				else
					begin
						mid_of_mid<=mid_x1;
					end
			end

end
/****Delay Signals************************/
always @ (posedge vclk)
begin
	vsync_reg <= vsync;
	hsync_reg <= hsync;
	vden_reg  <= vden;
end

assign vsync_out = vsync_reg;
assign hsync_out = hsync_reg;
assign vden_out  = vden_reg;
/****Delay Signals************************/
endmodule

/*
	求最大值中的最小值。
*/
`timescale 1ns/1ps

module min_of_3(
	//input
	vclk,
	vsync,
	hsync,
	vden,
	max_x1,
	max_x2,
	max_x3,
	//output
	vsync_out,
	hsync_out,
	vden_out,
	min_of_max
);
input vclk;
input vsync,hsync,vden;
input [23:0] max_x1,max_x2,max_x3;
output [23:0] min_of_max;
output vsync_out,hsync_out,vden_out;
reg [23:0] min_of_max=24'h0;
reg vsync_reg,hsync_reg,vden_reg;

always@(posedge vclk)
begin
	if(max_x1<max_x2)
		begin
			if(max_x3<max_x1)
				begin
					min_of_max<=max_x3;
				end
			else
				begin
					min_of_max<=max_x1;
				end
		end	
		else
			begin
				if(max_x3<max_x2)
				begin
					min_of_max<=max_x3;
				end
				else 
				begin
					min_of_max<=max_x2;
				end
			end
	
end

/****Delay Signals************************/
always @ (posedge vclk)
begin
	vsync_reg <= vsync;
	hsync_reg <= hsync;
	vden_reg  <= vden;
end

assign vsync_out = vsync_reg;
assign hsync_out = hsync_reg;
assign vden_out  = vden_reg;
/****Delay Signals************************/

endmodule

/*
	求最大值中的最小值。
*/
`timescale 1ns/1ps

module min_of_3(
	//input
	vclk,
	vsync,
	hsync,
	vden,
	max_x1,
	max_x2,
	max_x3,
	//output
	vsync_out,
	hsync_out,
	vden_out,
	min_of_max
);
input vclk;
input vsync,hsync,vden;
input [23:0] max_x1,max_x2,max_x3;
output [23:0] min_of_max;
output vsync_out,hsync_out,vden_out;
reg [23:0] min_of_max=24'h0;
reg vsync_reg,hsync_reg,vden_reg;

always@(posedge vclk)
begin
	if(max_x1<max_x2)
		begin
			if(max_x3<max_x1)
				begin
					min_of_max<=max_x3;
				end
			else
				begin
					min_of_max<=max_x1;
				end
		end	
		else
			begin
				if(max_x3<max_x2)
				begin
					min_of_max<=max_x3;
				end
				else 
				begin
					min_of_max<=max_x2;
				end
			end
	
end

/****Delay Signals************************/
always @ (posedge vclk)
begin
	vsync_reg <= vsync;
	hsync_reg <= hsync;
	vden_reg  <= vden;
end

assign vsync_out = vsync_reg;
assign hsync_out = hsync_reg;
assign vden_out  = vden_reg;
/****Delay Signals************************/

endmodule

/*	
	求中值的中值。
*/
`timescale 1ns/1ps

module mid_of_3(
	//input
	vclk,
	vsync,
	hsync,
	vden,
	mid_x1,
	mid_x2,
	mid_x3,
	//output
	vsync_out,
	hsync_out,
	vden_out,
	mid_of_mid
);
input vclk;
input vsync,hsyn