Computer Architecture Background

Overview

A computer’s main resources are memory and processors. On Intel computers, Dynamic Random Access Memory (DRAM) chips provide the memory, and one or more CPU chips expose logical processors.

System software uses virtualization techniques to isolate each piece of software that it manages (process or operating system) from the rest of the software running on the computer.

A key component of virtualization is address translation, which is used to give software the impression that it owns all the memory on the computer.

The other key component of virtualization is the software privilege levels enforced by the CPU.

Computational Model

A computer’s core is its processors and memory, which are connected by a system bus. Computers also have I/O devices, such as keyboards, which are also connected to the processor via the system bus.

Memory implements the abstraction depicted. Its salient feature is that the result of reading a memory cell at an address must equal the most value written to that memory cell.

Address Space

Software written for the Intel architecture accesses the computer’s resources using four distinct physical address spaces.*

The four physical address spaces used by an Intel CPU. The registers and MSRs are internal to the CPU, while the memory and I/O address spaces are used to communicate with DRAM and other devices via system buses.

Address Translation

Operating systems use address translation to implement the virtual memory abstraction.

Computers that take advantage of hardware virtualization use a hypervisor to run multiple operating systems at the same time. This creates some tension, because each operating system was written under the assumption that it owns the entire computer’s DRAM. The tension is solved by a second layer of address translation.

• Virtual Address -> Guest-Physical Addrsss (by Page Tables)
• Guest-Physical Address -> Physical Address (by Extended Page Tables (EPT) )

Execution Contexts

Application software targeting the 64-bit Intel architecture uses a variety of CPU registers to interact with the processor’s features. The values in these registers make up an application thread’s state, or execution context.

The Cores

Most Intel CPUs feature hyper-threading, which means that a core has two copies of the register files backing the execution context, and can execute two separate streams of instructions simultaneously. Hyper-threading reduces the impact of memory stalls on the utilization of the fetch, decode and execution units.

CPU core with two logical processors. Each logical processor has its own execution context and LAPIC. All the other core resources are shared.

Local Advanced Programmable Interrupt Controllers(LAPICs).

Cache

Cache and Memory-Mapped Devices

Cache and Address Translation

TLB

必须明确在分页机制中，TLB中的数据和页表中的数据的相关性，不是由处理器进行维护，而是必须由操作系统来维护，高速缓存的刷新是通过装入处理器（80386）中的寄存器CR3来完成的。