Armv8里定义的Cache的管理的操作有三种:
- 无效(Invalidate) 整个高速缓存或者某个高速缓存行。高速缓存上的数据会被丢弃。
- 清除(Clean) 整个高速缓存或者某个高速缓存行。相应的高速缓存行会被标记为脏,数据会写回到下一级高速缓存中或者主存储器中。
- 清零(Zero) 在某些情况下,对高速缓存进行清零操作起到一个预取和加速的功效,比如当程序需要使用一大块临时内存,在初始化阶段对这个内存进行清零操作,这时高速缓存控制器会主动把这些零数据写入高速缓存行中。若程序主动使用高速缓存的清零操作,那么将大大减少系统内部总线的带宽。
对高速缓存的操作可以指定不同的范围。
- 整块高速缓存。
- 某个虚拟地址。
- 特定的高速缓存行或者组和路。
另外在ARMv8架构中最多可以支持7级的高速缓存,L1~L7高速缓存。当对一个高速缓存行进行操作时,我们需要知道高速缓存操作的范围。ARMv8架构中从处理器到所有内存的角度分成如下几个视角。
- PoC(Point of Coherency,全局缓存一致性角度)
- PoU(Point of Unification,处理器缓存一致性角度
有了上面的这些概念,然后我们再看下cache的指令格式:
function中的G和D一般和其它function组合使用的,例如
DC IGDVAC :操作d-cache,根据虚拟地址无效掉data和Allocation Tags,操作范围到PoCInvalidate data and Allocation Tags in data cache by address to Point of Coherency.
DC IGVAC :操作d-cache,根据虚拟地址无效掉Allocation Tags,操作范围到PoC
Invalidate Allocation Tags in data cache by address to Point of Coherency
最后,我们再看armv8文档中定义的cache指令集:
DC CISW, Data or unified Cache line Clean and Invalidate by Set/Way DC CSW, Data or unified Cache line Clean by Set/Way DC CVAU, Data or unified Cache line Clean by VA to PoU DC ZVA, Data Cache Zero by VA IC IALLU, Instruction Cache Invalidate All to PoU IC IALLU{, <Xt>} IC IALLUIS, Instruction Cache Invalidate All to PoU, Inner Shareable IC IALLUIS{, <Xt>} IC IVAU, Instruction Cache line Invalidate by VA to PoU IC IVAU{, <Xt>} DC CIVAC, Data or unified Cache line Clean and Invalidate by VA to PoC DC CVAC, Data or unified Cache line Clean by VA to PoC DC CVAP, Data or unified Cache line Clean by VA to PoP DC GVA, Data Cache set Allocation Tag by VA DC GZVA, Data Cache set Allocation Tags and Zero by VA DC IGDSW, Data, Allocation Tag or unified Cache line Invalidate of Data and Allocation Tags by Set/Way DC IGDVAC, Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by VA to PoC DC IGSW, Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by Set/Way DC IGVAC, Data, Allocation Tag or unified Cache line Invalidate of Allocation Tags by VA to PoC DC ISW, Data or unified Cache line Invalidate by Set/Way DC IVAC, Data or unified Cache line Invalidate by VA to PoC DC CVADP, Data or unified Cache line Clean by VA to PoDP ARMv8.5-MemTag: DC CGDSW, Data, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by Set/Way DC CGDVAC, Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoC DC CGDVADP, Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoDP DC CGDVAP, Data, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by VA to PoP DC CGSW, Data, Allocation Tag or unified Cache line Clean of Allocation Tags by Set/Way DC CGVAC, Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoC DC CGVADP, Data, Allocation Tag or unified Cache line Clean of Data and Allocation Tags by VA to PoDP DC CGVAP, Data, Allocation Tag or unified Cache line Clean of Allocation Tags by VA to PoP DC CIGDSW, Data, Allocation Tag or unified Cache line Clean and Invalidate of Data and Allocation Tags by Set/Way DC CIGDVAC, Data, Allocation Tag or unified Cache line Clean and Invalidate of Data and Allocation Tags by VA to PoC DC CIGSW, Data, Allocation Tag or unified Cache line Clean and Invalidate of Allocation Tags by Set/Way DC CIGVAC, Data, Allocation Tag or unified Cache line Clean and Invalidate of Allocation Tags by VA to PoC
- cache操作的使用示例:
什么是PoU和PoC?
在cortex a7上看到PoC和PoU的概念如下:
PoC: the PoC is the point at which all blocks, for example, cores, DSPs, or DMA engines, that canaccess memory are guaranteed to see the same copy of a memory location.
PoU: the PoU for a core is the point at which the instruction and data caches of the core are guaranteed to see the same copy of a memory location.
1.感觉PoC和PoU只是看待内存的主体不一样而已,PoC是具体的agent看同一块内存的数据应该保持一致,而PoU是指的cache L1看同一块内存的数据应该保持一致,这样理解对么?
2.还有就是什么地方会用到PoC和PoU的概念呢?
Best Wishes,
larry
Hi Larry,
PoU和PoC的概念可以用下面的图片形象地描述:
PoU:(注:PoU的观测主体还包括TLB)
PoC:
> 1.感觉PoC和PoU只是看待内存的主体不一样而已,PoC是具体的agent看同一块内存的数据应该保持一致,
> 而PoU是指的cache L1看同一块内存的数据应该保持一致,这样理解对么?
可以这样理解。
>2.还有就是什么地方会用到PoC和PoU的概念呢?
在cache maintenance operation里会用到。你会看到这样的指令:
<operation> to PoU
<operation> to PoC
每个处理器的PoC/PoU位置不尽相同。对于Cortex-A7而言,假设已经配置了内嵌L2 cache,则:
- PoU位于L2 cache
- PoC位于ACE master interface
BR,
Xingguang Feng