因项目需要采集一个脉冲宽度7ns的脉冲计数功能,单片机速度无法实现,使用性价比比较高的CPLD EPM240。之前没有接触CPLD,verilog语法不熟悉,所以顶层使用硬件思维连线。实现功能。
EPM240分为4个模块
脉冲计数模块
module cnt(pulse,cntout,rst_n);
input pulse; //检测的脉冲信号
input rst_n; //检测控制引脚,高计数,低复位
output [31:0] cntout ;
reg [31:0] cnt,cntout;
always @( posedge pulse ,negedge rst_n)
begin
if(rst_n==0)
cnt <= 0;
else
begin
cnt <= cnt+1;
cntout = cnt;
end
end
endmodule
定时器1us 1ms
module us_ms
(
input clk, //系统晶振50MHz
input rst, //系统复位
output reg clk_1us, //输出频率1us时钟
output reg clk_1ms //输出频率1ms时钟
);
reg [32:0]cnt_us;
reg [32:0]cnt_ms;
always @(posedge clk or negedge rst)
begin
if (!rst)
begin
cnt_us <= 0;
clk_1us <= 0;
end
else if (cnt_us ==50)
begin
cnt_us <= 0;
clk_1us <= ~clk_1us;
end
else
begin
cnt_us <= cnt_us + 1;
end
end
always @(posedge clk or negedge rst) begin
if (!rst)
begin
cnt_ms <= 0;
clk_1ms <= 0;
end
else if (cnt_ms ==50000)
begin
cnt_ms <= 0;
clk_1ms <= ~clk_1ms;
end
else
begin
cnt_ms <= cnt_ms + 1;
end
end
endmodule
SPI从机通讯,只需要SPI发送数据,因此代码无接受数据代码
module spi(rst,clk,spi_mosi,spi_miso,spi_cs,sp_clk,din)
input rst; //系统复位
input clk; //系统时钟
input spi_mosi;//mcu发,fpga收
ouput reg spi_miso;//mcu收,fpga发
input spi_cs ;//spi片选
input spi_clk ;//spi时钟信号
input [31:0] spi_din;
reg spi_cs_reg,spi_cs_reg1;
reg spi_scl_reg,spi_scl_reg1;
reg scl_up_flag;
reg scl_down_flag;
always@(posedge clk)
begin
if(!rst)
begin
spi_cs_reg1<=0;
end
else
begin
spi_cs_reg1<=spi_cs;
end
end
always@(posedge clk)
begin
if(!rst)
begin
spi_cs_reg<=0;
end
else
begin
spi_cs_reg<=spi_cs_reg1;
end
end
always@(posedge clk)
begin
if(!rst)
begin
spi_scl_reg1<=0;
end
else
begin
spi_scl_reg1<=spi_scl;
end
end
always@(posedge clk)
begin
if(!rst)
begin
spi_scl_reg<=0;
end
else
begin
spi_scl_reg<=spi_scl_reg1;
end
end
//时钟线上升沿判断
always@(posedge clk)
begin
if(!rst)
begin
scl_up_flag<=0;
end
else
begin
if(spi_scl_reg1==1&&spi_scl_reg==0)
begin
scl_up_flag<=1;
end
else
begin
scl_up_flag<=0;
end
end
end
//spi时钟线下降沿判断
always@(posedge clk)
begin
if(!rst)
begin
scl_down_flag<=0;
end
else
begin
if(spi_scl_reg1==0&&spi_scl_reg==1)
begin
scl_down_flag<=1;
end
else
begin
scl_down_flag<=0;
end
end
end
// 发送数据
reg 31:0] din_reg; //发送数据的缓存器
always@(posedge clk)
begin
if(!rst)
begin
spi_miso<=0;
din_reg<=0;
end
else
begin
if(spi_cs_reg1==0&&spi_cs_reg==0)
begin
if(scl_down_flag)
begin
spi_miso<=din_reg[31];
din_reg[31:0]<={din_reg[30:0],1'b0};
end
else
begin
spi_miso<=spi_miso;
din_reg[31:0]<=din_reg[31:0];
end
end
else if(spi_cs_reg1==0&&spi_cs_reg==1)
begin
spi_miso<=spi_miso;
din_reg31:0]<=din[31:0];
end
else
begin
spi_miso<=spi_miso;
din_reg[31:0]<=din_reg[31:0];
end
end
end
endmodule