1. incorrect connector style at port "step1[15..0]" for symbol
解决方法:
CAUSE 1: | In a Graphic Design File (.gdf), there is a width mismatch between the line style of the connector and the specified port of the specified symbol. |
ACTION: | Change the line style to the appropriate width connector. |
CAUSE 2: | In a Graphic Design File (.gdf), a conduit is used to connect a symbol port directly. A symbol can be directly connected only to a node or bus line. |
ACTION: | Change the line style to bus if it is a bus port. Otherwise, change the line style to node. 通过改变线宽解决。 |
2. singal "clk" drives an input pin
解决方法:
CAUSE: | In a Graphic Design File (.gdf), the specified signal drives an input pin. However, an input pin cannot be driven by a signal. |
ACTION: | Specify a different name for the signal so that it does not drive an input pin. 同3,此信号错误的作为另外一个信号的驱动信号! |
3. Node line contains "sys_rst_b" and "clk", but may be named only once
解决方法:
CAUSE: | In a Graphic Design File (.gdf), a node line contains more than one name. However, single node lines not separated by connection dots can have only one name. |
ACTION: | insert a connection dot to separate the two signal names. 不小心把这2个连接在一起了!
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4. Port " " does not exist in macrofunction " "
解决办法:
CAUSE: | You connected the specified macrofunction to a lower-level macrofunction through the specified port that does not exist. As a result, the Quartus II software cannot compile the design. |
ACTION: | Remove the illegal connection or create a port for the lower-level macrofunction. 打开.bsf文件,发现Port名称为step_mot_init_en_b的另外一个text名称为“port“,导致报此错误!!! 修改名称为一致解决此问题。 |
5. can''t place 7 pins with 3.0-V LVTTL I/O standard because Fitter has only 0 such free pins available for general purpose I/O placement.
解决办法: 有7个Node没有管脚分配,但I /O Standard为3.0-V LVTTL。在Pin Planner中删除后再次打开还存在这些Note。然后删除框图中的所有相关Note命名,再次在Pin Planner中删除,然后针对Pin进行编译,通过。