遍历PCI总线并输出所有设备及其基址寄存器类型

#include "windows.h" #include "stdio.h" #include "rtapi.h" #define NO_ERRORS 0 PCI_SLOT_NUMBER SlotNumber; PPCI_COMMON_CONFIG PciData; UCHAR buffer[PCI_COMMON_HDR_LENGTH]; int main( int argc, char *argv[] ) { ULONG i; // logical slot number for the PCI adapter ULONG f; // function number on the specified adapter ULONG bytesWritten; // return value from RtGetBusDataByOffset ULONG bus; // bus number BOOLEAN flag; ULONG Offset= 0; ULONG nothingWritten = 0; ULONG dwTemp[PCI_TYPE0_ADDRESSES]; ULONG idx; LARGE_INTEGER BusAddr; ULONG AddressSpace; LARGE_INTEGER TranslatedAddr; PciData = (PPCI_COMMON_CONFIG) buffer; SlotNumber.u.bits.Reserved = 0; flag = TRUE; for (bus=0; flag; bus++) { for (i=0; i<PCI_MAX_DEVICES && flag; i++) { SlotNumber.u.bits.DeviceNumber = i; for (f=0; f<PCI_MAX_FUNCTION; f++) { SlotNumber.u.bits.FunctionNumber = f; bytesWritten = RtGetBusDataByOffset ( PCIConfiguration, bus, SlotNumber.u.AsULONG, PciData, Offset, PCI_COMMON_HDR_LENGTH ); if (bytesWritten == nothingWritten) { // out of PCI buses flag = FALSE; break; } if (PciData->VendorID == PCI_INVALID_VENDORID) { // no device at this slot number, skip to next slot break; } if (PciData->u.type0.InterruptPin == 0) { // no pin number for this device - it was simply // illusion that it exists break; } // // A device is found, print out the PCI configuration information // printf("/n/n -------------------------PciData: -------------------------/n"); printf("BusNumber:/t/t%d/n", bus); printf("DeviceNumber:/t/t%d/n", i); printf("FunctionNumber:/t/t%d/n", f); printf("VendorID:/t/t0x%x/n", PciData->VendorID); printf("DeviceID:/t/t0x%x/n", PciData->DeviceID); printf("Command:/t/t0x%x/n", PciData->Command); printf("Status:/t/t/t0x%x/n", PciData->Status); printf("RevisionID:/t/t0x%x/n", PciData->RevisionID); printf("ProgIf:/t/t/t0x%x/n", PciData->ProgIf); printf("SubClass:/t/t0x%x/n", PciData->SubClass); printf("BaseClass:/t/t0x%x/n", PciData->BaseClass); printf("CacheLineSize:/t/t0x%x/n", PciData->CacheLineSize); printf("LatencyTimer:/t/t0x%x/n", PciData->LatencyTimer); printf("HeaderType:/t/t0x%x/n", PciData->HeaderType); printf("BIST:/t/t/t0x%x/n", PciData->BIST); for (idx=0;idx<=5;idx++) { printf("/n**** BaseAddr[%d]", idx); BusAddr.QuadPart = PciData->u.type0.BaseAddresses[idx]; AddressSpace = 1; // 0x0 indicates memory 0x1 indicates I/O space if (!RtTranslateBusAddress( PCIBus, bus, BusAddr, &AddressSpace,&TranslatedAddr)) { printf ("/n error translating bus port address./n"); return ; } dwTemp[idx] = TranslatedAddr.LowPart; printf("/n Translated Addr /t0x%08x ->/t0x%08x",PciData->u.type0.BaseAddresses[idx], dwTemp[idx]); /* 在所有的基址寄存器中，位0均为只读位并且用来决定能够是存储器空间还是I/O空间。 如果该位为0，则表示映射到存储器空间；若为1则表示映射到I/O地址空间。 */ if ((dwTemp[idx] & 0x00000001) == 0x00000000){ printf("/t---- IS MEMO"); } else{ printf("/t---- IS IO"); } } } } } return NO_ERRORS; }  

 

某台式机上测试结果如下：

 

 

 -------------------------PciData: -------------------------

BusNumber: 0

DeviceNumber: 2

FunctionNumber: 0

VendorID: 0x8086

DeviceID: 0x2572

Command: 0x7

Status: 0x90

RevisionID: 0x2

ProgIf: 0x0

SubClass: 0x0

BaseClass: 0x3

CacheLineSize: 0x0

LatencyTimer: 0x0

HeaderType: 0x0

BIST: 0x0

**** BaseAddr[0]

 Translated Addr 0xe8000008 -> 0xe8000008 ---- IS MEMO

**** BaseAddr[1]

 Translated Addr 0xfeb80000 -> 0xfeb80000 ---- IS MEMO

**** BaseAddr[2]

 Translated Addr 0x0000ed99 -> 0x0000ed99 ---- IS IO

**** BaseAddr[3]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[4]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[5]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

 -------------------------PciData: -------------------------

BusNumber: 0

DeviceNumber: 29

FunctionNumber: 0

VendorID: 0x8086

DeviceID: 0x24d2

Command: 0x5

Status: 0x280

RevisionID: 0x2

ProgIf: 0x0

SubClass: 0x3

BaseClass: 0xc

CacheLineSize: 0x0

LatencyTimer: 0x0

HeaderType: 0x80

BIST: 0x0

**** BaseAddr[0]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[1]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[2]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[3]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[4]

 Translated Addr 0x0000ff81 -> 0x0000ff81 ---- IS IO

**** BaseAddr[5]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

 -------------------------PciData: -------------------------

BusNumber: 0

DeviceNumber: 29

FunctionNumber: 1

VendorID: 0x8086

DeviceID: 0x24d4

Command: 0x5

Status: 0x280

RevisionID: 0x2

ProgIf: 0x0

SubClass: 0x3

BaseClass: 0xc

CacheLineSize: 0x0

LatencyTimer: 0x0

HeaderType: 0x0

BIST: 0x0

**** BaseAddr[0]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[1]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[2]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[3]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[4]

 Translated Addr 0x0000ff61 -> 0x0000ff61 ---- IS IO

**** BaseAddr[5]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

 -------------------------PciData: -------------------------

BusNumber: 1

DeviceNumber: 8

FunctionNumber: 0

VendorID: 0x8086

DeviceID: 0x1050

Command: 0x117

Status: 0x290

RevisionID: 0x2

ProgIf: 0x0

SubClass: 0x0

BaseClass: 0x2

CacheLineSize: 0x10

LatencyTimer: 0x40

HeaderType: 0x0

BIST: 0x0

**** BaseAddr[0]

 Translated Addr 0xfeaff000 -> 0xfeaff000 ---- IS MEMO

**** BaseAddr[1]

 Translated Addr 0x0000df41 -> 0x0000df41 ---- IS IO

**** BaseAddr[2]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[3]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[4]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO

**** BaseAddr[5]

 Translated Addr 0x00000000 -> 0x00000000 ---- IS MEMO