--/*******************************************************************
-- *
-- *
-- * AUTHOR:
-- *
-- * HISTORY:
-- *
-- *******************************************************************/
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY ScanKey IS
PORT (clk,reset : IN std_logic;
KeyIn : IN std_logic_vector(3 downto 0);
led : OUT std_logic_vector(3 downto 0);
KeyOut : OUT std_logic_vector(1 downto 0));
END ScanKey;
ARCHITECTURE behave OF ScanKey IS
SIGNAL led_reg : std_logic_vector(3 downto 0);
SIGNAL KeyOut_reg : std_logic_vector(1 downto 0);
SIGNAL clk_div : std_logic;
SIGNAL Key_reg : std_logic_vector(3 downto 0);
SIGNAL KeyIn_reg : std_logic_vector(3 downto 0);
SIGNAL clk_div_s : std_logic;
CONSTANT CLK_DIV_RANGE :integer := 16384;
CONSTANT CLK_DIV_C :integer := 100